ACE25QC160GLDPTH datasheet(12/73 Pages) ACE

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ACE25QC160G

16M BIT SPI NOR FLASH

VER 1.2

(G)

CMP bit

The CMP bit is a non-volatile Read/Write bit in the Status Register (S14). It is used in conjunction the

SEC-BP0 bits to provide more flexibility for the array protection. Please see the Status registers

Memory Protection table for details. The default setting is CMP=0.

(H)

SUS1/SUS2 bit

The SUS1 and SUS2 bits are read only bits in the status register2 (S15 and S10) that are set to 1 after

executing an Erase/Program Suspend (75H) instruction (The Erase Suspend will set SUS1 to 1, and

the Program Suspend will set the SUS2 to 1). The SUS1 and SUS2 bits are cleared to 0 by

Erase/Program Resume (7AH) instruction as well as a power-down, power-up cycle.

(I)

DRV1/DRV0

The DRV1&DRV0 bits are used to determine the output driver strength for the Read instruction.

DRV1,DRV0

Driver Strength

100%(default)

75%

50%

25%

Status Register Protect Table

The Status Register Protect (SRP1 and SRP0) bita are non-volatile Read/Write bits in the Status Register.

The SRP bits control the morhod of write protection: software protection, hardware protection, power

supply lock-down or one time programmable protection.

Table4. ACE25QC160G Status Register protect table

SRP1

SRP0

/WP

Status Register

Description

Software Protected

The Status Register can be written to after a

Write Enable instruction, WEL=1.(Factory

Default)

Hardware Protected

/WP=0, the Status Register locked and

cannot be written.

Hardware Unprotected

/WP=1, the Status Register is unlocked and

can be written to after a Write Enable

instruction, WEL=1.

Power Supply Lock-Down(1)

Status Register is protected and cannot be

written to again until the next Power-Down,

Power-Up cycle.

One Time Program(2)

Status Register is permanently protected and

cannot be written to.

Notes:

When SRP1, SRP0= (1, 0), a Power-Down, Power-Up cycle will change SRP1, SRP0 to (0, 0) state.

The One time Program feature is available upon special order.

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