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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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ACE25QC160GLDPTH датащи(PDF) 28 Page - ACE Technology Co., LTD. |
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ACE25QC160GLDPTH датащи(HTML) 28 Page - ACE Technology Co., LTD. |
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28 / 73 page  ACE25QC160G 16M BIT SPI NOR FLASH VER 1.2 28 Fast Read (0Bh) in QPI Mode The Fast Read instruction is also supported in QPI mode. When QPI mode is enabled, the number of dummy clocks is configured by the “Set Read Parameters (C0h)” instruction to accommodate a wide range of applications with different needs for either maximum Fast Read frequency or minimum data access latency. Depending on the Read Parameter Bits P[5:4] setting, the number of dummy clocks can be configured as either 2, 4, 6 or 8. The default number of dummy clocks upon power up or after a Reset instruction is 2. Dual Output Fast Read (3BH) See Figure 9, the Dual Output Fast Read instruction is followed by 3-byte address (A23-A0) and a dummy byte, each bit being latched in during the rising edge of SCLK, then the memory contents are shifted out 2-bit per clock cycle from SI and SO. The first byte addressed can be at any location. The address is automatically incremented to the next higher address after each byte of data is shifted out. Figure9. Dual Output Fast Read Sequence Diagram (SPI Mode only) Figure8 b. Fast Read Sequence Diagram (QPI Mode) |
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