ACE25QC160GLDPTH datasheet(48/73 Pages) ACE

48 / 73 page

ACE25QC160G

16M BIT SPI NOR FLASH

VER 1.2

Program Security Registers (42H)

See Figure 29, the Program Security Registers instruction is similar to the Page Program instruction. It

allows from 1 to 256 bytes Security Registers data to be programmed. A Write Enable instruction must

previously have been executed to set the Write Enable Latch bit before sending the Program Security

Registers instruction. The Program Security Registers instruction is entered by driving /CS Low, followed

by the instruction code (42H), 3-byte address and at least one data byte on SI. As soon as /CS is driven

high, the self-timed Program Security Registers cycle (whose duration is tPP) is initiated. While the

Program Security Registers cycle is in progress, the Status Register may be read to check the value of the

Write In Progress (WIP) bit. The Write In Progress (WIP) bit is 1 during the self-timed Program Security

Registers cycle, and is 0 when it is completed. At some unspecified time before the cycle is completed, the

Write Enable Latch bit is reset.

If the Security Registers Lock Bit (LB3/LB2/LB1) is set to 1, the Security Registers will be permanently

locked. Program Security Registers instruction will be ignored.

Address

A23-A16

A15-A12

A11-A8

A7-A0

Security Registers 1

00H

0001

0000

Byte Address

Security Registers 2

00H

0010

0000

Byte Address

Security Registers 3

00H

0011

0000

Byte Address

Figure29. Program Security Registers instruction Sequence Diagram (SPI Mode only)

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