ACE25QC160GLDPTH datasheet(29/73 Pages) ACE

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ACE25QC160G

16M BIT SPI NOR FLASH

VER 1.2

Quad Output Fast Read (6BH)

See Figure 10, the Quad Output Fast Read instruction is followed by 3-byte address (A23-A0) and a

dummy byte, each bit being latched in during the rising edge of SCLK, then the memory contents are shifted

out 4-bit per clock cycle from IO3, IO2, IO1 and IO0. The first byte addressed can be at any location. The

address is automatically incremented to the next higher address after each byte of data is shifted out.

Dual I/O Fast Read (BBH)

See Figure 11, the Dual I/O Fast Read instruction is similar to the Dual Output Fast Read instruction but

with the capability to input the 3-byte address (A23-0) and a “Continuous Read Mode” byte 2-bit per clock

by SI and SO, each bit being latched in during the rising edge of SCLK, then the memory contents are

shifted out 2-bit per clock cycle from SI and SO. The first byte addressed can be at any location. The

address is automatically incremented to the next higher address after each byte of data is shifted out.

Dual I/O Fast Read with “continuous Read Mode”

The Dual I/O Fast Read instruction can further reduce instruction overhead through setting the “continuous

Read Mode “bits (M7-4) after the inputs 3-byte address A23-A0).If the “continuous Read Mode

“bits(M5-4)=(1,0),then the next Dual I/O fast Read instruction (after CS/ is raised and then lowered) does

not require the BBH instruction code. The instruction sequence is shown in the following Figure 12.If the

“continuous Read Mode “bits (M5-4) does not equal (1,0),the next instruction requires the first BBH

instruction code, thus returning to normal operation. A “continuous Read Mode” Reset instruction can be

used to reset (M5-4) before issuing normal instruction.

Figure10. Quad Output Fast Read Sequence Diagram (SPI Mode only)

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