ACE25QC160GLDPTH datasheet(10/73 Pages) ACE

10 / 73 page

ACE25QC160G

16M BIT SPI NOR FLASH

VER 1.2

Hold Condition

The Hold (/HOLD) signal is used to pause any serial communications with the device without resetting the

clocking sequence. During the Hold condition, the Serial Data Output (SO) is high impedance, and Serial

Data Input (SI) and Serial Clock (SCLK) are Don’t Care. To enter the Hold condition, the device must be

selected, with Chip Select (/CS) Low. Normally, the device is kept selected, for the whole duration of the

Hold condition. Deselecting the device while it is in the Hold condition, has the effect of resetting the state

of the device, and this mechanism can be used if it is required to reset any processes that had been in

progress.

The Hold condition starts when the Hold (/HOLD) signal is driven Low at the same time as Serial Clock

(SCLK) already being Low (as shown in Figure 1).

The Hold condition ends when the Hold (HOLD) signal is driven High at the same time as Serial Clock (C)

already being Low. Figure 1 also shows what happens if the rising and falling edges are not timed to

coincide with Serial Clock (SCLK) being Low.

Status Register

Status Register Table

See Table 3 for detail description of the Status Register bits.

Table3. Status Register

S23

S22

S21

S20

S19

S18

S17

S16

Reserved

DRV1

DRV0

Reserved

S15

S14

S13

S12

S11

S10

SUS1

CMP

LB3

LB2

LB1

SUS2

SRP1

SRP0

BP4

BP3

BP2

BP1

BP0

WEL

WIP

Figure1. Hold condition activation

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