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17

FBS-GAM02-P-R50 Datasheet

Interfacing the FBS-GAM02 to Legacy Rad-Hard PWM Controllers (continued)

b.) Zener diode voltage clamp with ASIC/FPGA Two-Phase PWM Generator.

The same Zener diode clamping circuit as shown in Figure 14 may be used to clamp the output of the UC1823A to a lower voltage level

FBS-GAM02-P-R50. A typical circuit for this circuit implementation is shown in Figure 15:

In the circuit of Figure 15 all the high-speed and high accuracy analog functions associated with the PWM controller are performed off-

chip from the FPGA/ASIC. The programmable logic of the FPGA/ASIC and the associated firmware code is responsible for generating

Figure 15. Zener Diode Logic Input Voltage Clamp Circuit with

ASIC/FPGA Two-Phase Clock (With Dead Time) Generator

VC

PGND

UC1823A-SP

FPGA/

ASIC

OUT

GP01

GP02

GPI

D1

D4

CC

R1

R2