FBSGAM02PR50 datasheet(16/33 Pages) EPC-CO

16 / 33 page

EPC.SPACE

FBS-GAM02-P-R50 Datasheet

Interfacing the FBS-GAM02 to Legacy Rad-Hard PWM Controllers

The BIN and TIN logic inputs for the FBS-GAM02-P-R50 have a desired maximum input voltage level limit of 5 VDC due to the

requirements of the eGaN HEMT technology utilized in the Module. This may seem to preclude the use of the GAM02 with legacy rad-

hard PWM controllers such as the 182X family -- whose PWM outputs are 12 VDC, minimum -- due to this logic input voltage limitation.

But this is not the case as there are several ways to interface the GAM02 to these controllers:

a.) Zener diode voltage clamp with dead-time generation circuit

A Zener diode may be used to clamp the BIN and TIN logic inputs of the FBS-GAM02-P-R50 in order to interface the module to a high

output voltage level PWM controller, as shown in Figure 14. The output of the UC1823A is a totem-pole configuration, and the output

switches between 0 VDC and 12 VDC as logic 0 and logic 1, respectively. The transition times between logic states for a 1000 pF load are

typically 20 ns, but much faster with lighter loads.

The nominal voltage of the Zener diode, D4, should be 2.7 VDC if U1 through U3 are 3.0 or 3.3 VDC CMOS logic, and 4.3 VDC if U1 though

U3 are 5.0 VDC CMOS logic. Depending upon the Zener diode chosen, the junction capacitance can be quite high – in the range of 250

to 500 pF. This is far greater than the typical input capacitance of the GAM02, which is 7 pF, and thus must be compensated for. Select

capacitor CC, the speed-up capacitor, to achieve the fastest rise time at the input of U1. Select R1 to limit the minimum current through

Zener D4 to be the nominal Zener current. Select R2 to limit the peak Zener current to less than the Zener peak current rating. Schottky

diodes D1 through D3 are types RB751S40 or equivalent. Logic gates U1 and U2 are high-speed buffers, preferably with Schmitt-

trigger inputs and logic gate U3 is a high-speed inverter, again preferably with Schmitt-trigger input. These three logic gates, along with

resistors RD1 and RD2 and capacitors CD1 and CD2 form the dead-time circuit required for the GAM02 when it is connected in the

half-bridge configuration, such as for the power output stage of a POL DC-DC converter. In the circuit, resistor RD1 and capacitor CD1

implement the time delay td1 and RD2 and CD2 implement the time delay td2 (see Notes 12 and 21). Set RD1 and RD2 to 1 kΩ and then

select CD1 and CD2 to obtain time delays tD1 and tD2 as shown in the “Half-Bridge Configuration Dynamic Electrical Characteristics”

parametric table on page 5. All component values and performance criteria should be verified with simulation modeling.

Figure 14. Zener Diode Logic Input Voltage Clamp Circuit and Dead Time Delay Circuit

+12 VDC

PGND

UC1823A-SP

OUT

TIN

BIN

RD2

RD1

CD1

CD2

FBSGAM02PR50 датащи(PDF) 16 Page - Efficient Power Conversion Corporation.