M50FLW040A datasheet(14/52 Pages) STMICROELECTRONICS

14 / 52 page

M50FLW040A, M50FLW040B

14/52

Table 6. FWH Bus Read Field Definitions

Figure 7. FWH Bus Read Waveforms

Clock

Cycle

Number

Clock

Cycle

Count

Field

FWH0-

FWH3

Memory

I/O

Description

START

1101b

On the rising edge of CLK with FWH4 Low, the contents of FWH0-

FWH3 indicate the start of a FWH Read cycle.

IDSEL

XXXX

Indicates which FWH Flash Memory is selected. The value on

FWH0-FWH3 is compared to the IDSEL strapping on the FWH

Flash Memory pins to select which FWH Flash Memory is being

addressed.

3-9

ADDR

XXXX

A 28-bit address is transferred, with the most significant nibble

first. For the multi-byte read operation, the least significant bits

(MSIZE of them) are treated as Don’t Care, and the read operation

is started with each of these bits reset to 0. Address lines A19-21

and A23-27 are treated as Don’t Care during a normal memory

array access, with A22=1, but are taken into account for a register

access, with A22=0. (See Table 15.)

MSIZE

XXXX

This one clock cycle is driven by the host to determine the number

of Bytes that will be transferred. M50FLW040 supports: single

Byte transfer (0000b), 2-Byte transfer (0001b), 4-Byte transfer

(0010b), 16-Byte transfer (0100b) and 128-Byte transfer (0111b).

TAR

1111b

The host drives FWH0-FWH3 to 1111b to indicate a turnaround

cycle.

TAR

1111b

(float)

The FWH Flash Memory takes control of FWH0-FWH3 during this

cycle.

13-14

WSYNC

0101b

The FWH Flash Memory drives FWH0-FWH3 to 0101b (short

wait-sync) for two clock cycles, indicating that the data is not yet

available. Two wait-states are always included.

RSYNC

0000b

The FWH Flash Memory drives FWH0-FWH3 to 0000b, indicating

that data will be available during the next clock cycle.

16-17

M=2n

DATA

XXXX

Data transfer is two CLK cycles, starting with the least significant

nibble. If multi-Byte read operation is enabled, repeat cycle-16 and

cycle-17 n times, where n = 2MSIZE.

TAR

1111b

The FWH Flash Memory drives FWH0-FWH3 to 1111b to indicate

a turnaround cycle.

1TAR

1111b

(float)

N/A

The FWH Flash Memory floats its outputs, the host takes control

of FWH0-FWH3.

AI08433B

CLK

FWH4

FWH0-FWH3

Number of

clock cycles

START

IDSEL

ADDR

MSIZE

TAR

SYNC

DATA

TAR

117123

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