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PRELIMINARY DATA

August 2004

This is preliminary information on a new product now in development or undergoing evaluation. Details are subject to change without notice.

M50FLW040A

M50FLW040B

4 Mbit (5 x 64KByte Blocks + 3 x 16 x 4KByte Sectors)

3V Supply Firmware Hub / Low Pin Count Flash Memory

FEATURES SUMMARY

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FLASH MEMORY

–

Compatible with either the LPC interface

or the FWH interface (Intel Spec rev1.1)

used in PC BIOS applications

–

5 Signal Communication Interface

supporting Read and Write Operations

–

5 Additional General Purpose Inputs for

platform design flexibility

–

Synchronized with 33MHz PCI clock

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8 BLOCKS OF 64 KBYTES

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5 blocks of 64 KBytes each

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3 blocks, subdivided into 16 uniform

sectors of 4 KBytes each

Two blocks at the top and one at the

bottom (M50FLW040A)

One block at the top and two at the bottom

(M50FLW040B)

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ENHANCED SECURITY

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Hardware Write Protect Pins for Block

Protection

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Register-based Read and Write

Protection

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SUPPLY VOLTAGE

Read Operations

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TWO INTERFACES

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Auto Detection of Firmware Hub (FWH) or

Low Pin Count (LPC) Memory Cycles for

Embedded Operation with PC Chipsets

–

Address/Address Multiplexed (A/A Mux)

Interface for programming equipment

compatibility.

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PROGRAMMING TIME: 10µs typical

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PROGRAM/ERASE CONTROLLER

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Embedded Program and Erase algorithms

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Status Register Bits

Figure 1. Packages

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PROGRAM/ERASE SUSPEND

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Read other Blocks/Sectors during

Program Suspend

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Program other Blocks/Sectors during

Erase Suspend

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ELECTRONIC SIGNATURE

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Manufacturer Code: 20h

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Device Code (M50FLW040A): 08h

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Device Code (M50FLW040B): 28h

TSOP32 (NB)

8 x 14mm

PLCC32 (K)

TSOP40 (N)

10 x 20mm