M50FLW040A datasheet(13/52 Pages) STMICROELECTRONICS

13 / 52 page

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M50FLW040A, M50FLW040B

See Table 7. and Table 9., and Figure 8. and Fig-

ure 10., for a description of the Field definitions for

each clock cycle of the transfer. See Table 26.,

and Figure 15., for details on the timings of the sig-

nals.

Bus Abort. The Bus Abort operation can be used

to abort the current bus operation immediately. A

Bus Abort occurs when FWH4/LFRAME is driven

Low, VIL, during the bus operation. The device

puts

the

Input/Output

Communication

pins,

FWH0/LAD0-FWH3/LAD3, to high impedance.

Note that, during a Bus Write operation, the Com-

mand Interface starts executing the command as

soon as the data is fully received. A Bus Abort dur-

ing the final TAR cycles is not guaranteed to abort

the command. The bus, however, will be released

immediately.

Standby. When FWH4/LFRAME is High, VIH, the

device is put into Standby mode, where FWH0/

LAD0-FWH3/LAD3 are put into a high-impedance

state and the Supply Current is reduced to the

Standby level, ICC1.

Reset. During the Reset mode, all internal circuits

are switched off, the device is deselected, and the

outputs are put to high-impedance. The device is

in the Reset mode when Interface Reset, RP, or

CPU Reset, INIT, is driven Low, VIL. RP or INIT

must be held Low, VIL, for tPLPH. The memory re-

verts to the Read mode upon return from the Re-

set mode, and the Lock Registers return to their

default states regardless of their states before Re-

set. If RP or INIT goes Low, VIL, during a Program

or Erase operation, the operation is aborted and

the affected memory cells no longer contain valid

data. The device can take up to tPLRH to abort a

Program or Erase operation.

Block Protection. Block

Protection

can

forced using the signals Top Block Lock, TBL, and

Write Protect, WP, regardless of the state of the

Lock Registers.

Address/Address Multiplexed (A/A Mux) Bus

Operations

The Address/Address Multiplexed (A/A Mux) Inter-

face has a more traditional-style interface. The sig-

nals consist of a multiplexed address signals (A0-

A10), data signals, (DQ0-DQ7) and three control

signals (RC, G, W). An additional signal, RP, can

be used to reset the memory.

The Address/Address Multiplexed (A/A Mux) Inter-

face is included for use by Flash Programming

equipment for faster factory programming. Only a

subset of the features available to the Firmware

Hub (FWH)/Low Pin Count (LPC) Interface are

available; these include all the Commands but ex-

clude the Security features and other registers.

The following operations can be performed using

the appropriate bus cycles: Bus Read, Bus Write,

Output Disable and Reset.

When the Address/Address Multiplexed (A/A Mux)

Interface is selected, all the blocks are unprotect-

ed. It is not possible to protect any blocks through

this interface.

Bus Read. Bus Read operations are used to read

the contents of the Memory Array, the Electronic

Signature or the Status Register. A valid Bus Read

operation begins by latching the Row Address and

Column Address signals into the memory using

the Address Inputs, A0-A10, and the Row/Column

Address Select RC. Write Enable (W) and Inter-

face Reset (RP) must be High, VIH, and Output

Enable, G, Low, VIL. The Data Inputs/Outputs will

output the value, according to the timing con-

straints specified in Figure 17., and Table 28..

Bus Write. Bus Write operations are used to write

to the Command Interface. A valid Bus Write oper-

ation begins by latching the Row Address and Col-

umn Address signals into the memory using the

Address Inputs, A0-A10, and the Row/Column Ad-

dress Select RC. The data should be set up on the

Data Inputs/Outputs; Output Enable, G, and Inter-

face Reset, RP, must be High, VIH; and Write En-

able, W, must be Low, VIL. The Data Inputs/

Outputs are latched on the rising edge of Write En-

able, W. See Figure 18., and Table 29., for details

of the timing requirements.

Output Disable. The data outputs are high-im-

pedance when the Output Enable, G, is at VIH.

Reset. During the Reset mode, all internal circuits

are switched off, the device is deselected, and the

outputs are put at high-impedance. The device is

in the Reset mode when RP is Low, VIL. RP must

be held Low, VIL for tPLPH. If RP goes Low, VIL,

during a Program or Erase operation, the opera-

tion is aborted, and the affected memory cells no

longer contain valid data. The memory can take up

to tPLRH to abort a Program or Erase operation.

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