L9026 datasheet(19/60 Pages) STMICROELECTRONICS

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Parameter

Description

Test condition

Min Typ

Max

Unit

VDDIO pin

VDDIO(OP)

Logic Supply Operating

range voltage

fCLK = 8 MHz

5.5

VDDIO(UV_RECOVERY)

Analog supply threshold

for recovery after battery

undervoltage

MISO from “low” to high impedance

2.7 2.85

VDDIO(UV)

Undervoltage shutdown

MISO from “low” to high impedance

2.65 2.8

2.95

IVDDIO(SLEEP)

Logic supply current in

Sleepmode

VIDLE = 0; VINn = 0; VDDIO = 5 VTJ ≤ 85 °C

µA

IVDDIO(SLEEP)

Logic supply current in

Sleep mode

VIDLE = 0V; VINn = 0 V; VDDIO = 5 VTJ ≤ 150

°C

µA

IVDDIO(IDLE)

Logic supply current in

Idle Mode

VIDLE = 5 V; VINn = 0 V; VDDIO = 5 V; fCLK = 0

MHz; CFG_1.ACT = 0B; PWM_SPI.OUTn = 0B;

DIAG_OFF_EN.OUTn = 0B

1.2

IVDDIO(IDLE)

Logic supply current in

Idle mode (COR)

VIDLE = 5 V; VINn = 0 V; VDDIO = 5 V; fCLK = 0

MHz; CFG_1.ACT = 0B; PWM_SPI.OUTn = 0B;

DIAG_OFF_EN.OUTn = 0B; VBATT = VDDIO -

1 V

IVDDIO(ACTIVE)

Logic supply current in

Active mode – channels

OFF

VIDLE = 5 V; VINn = 0 V; VDDIO = 5 V; fCLK = 0

MHz; CFG_1.ACT = 1B; PWM_SPI.OUTn = 0B;

DIAG_OFF_EN.OUTn = 0B

0.95

1.5

IVDDIO(ACTIVE_COR)

Logic supply current in

Active mode – channels

OFF (COR)

VIDLE = 5 V; VINn = 0 V; VDDIO = 5 V; fCLK = 0

MHz; CFG_1.ACT = 1B; PWM_SPI.OUTn = 0B;

DIAG_OFF_EN.OUTn = 0B; VBATT = VDDIO -

1 V

tVDDIOUVFLT

VDDIO undervoltage

filter

Covered bySCAN

µs

Timings

tIDLEFLT

Idle filter time

µs

tSLEEP2IDLE

Sleep to Idle delay

µs

tIDLE2SLEEP

Idle to Sleep delay

from IDLE pin to sleep

External pull-down MISO to GND required

µs

tIDLE2ACTIVE

Idle to Active delay

from INn or NCS pins to MODE = 11B

µs

tACTIVE2IDLE

Active to Idle delay

from INn or NCS pins to MODE = 10B

150

µs

tSLEEP2LH

Sleep to Limp Home

delay

from INn pins to VDS = 10 % VBATT

10+tON

µs

tLH2SLEEP

Limp Home to Sleep

delay

from INn pins to MODE = 00B

External pull-down MISO to GND required.

150

µs

tLH2ACTIVE

Limp Home to Active

delay

from IDLE pin to MODE = 11B

µs

tACTIVE2LH

Active to Limp Home

delay

from IDLE pin to MODE = 01B

µs

tACTIVE2SLEEP

Active to Sleep delay

from IDLE pin to MODE = 00B

External pull-down MISO to GND required.

150

µs

L9026

Power supply electrical specifications

DS13397 - Rev 5

page 19/60

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