GC5316 datasheet(32/75 Pages) TI

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GC5316

SLWS154A − JANUARY 2004 − REVISED MARCH 2004

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The power measurement process starts with a sync event (ssel_pmeter). The integration starts at sync event + 3

chips + sync_delay. The 7-bit delay register permits delays from 3 to 130 samples after sync. The integration

continues until the integration count is met. At that point the top 32 bits of the 50-bit accumulator is transferred to

the read register and an interrupt is generated indicating the power value is ready to read. The interval counter

continues until the programmed interval count is reached. When reached, the integration counter and the interval

counter start over again. Each time the integration count is reached the upper 32 bits are again transferred to the

read register overwriting the previous value sending an interrupt signifying the data is ready to be read. Failure to

read the data timely results in overwriting the previous interval measurement.

Sync ssel_pmeter starts the process. Whenever a sync is received, all the counters are reset to zero no matter what

the status.

For UMTS, I and Q are calculated and the integrated power is read. When in CDMA mode the power is calculated

for both the A and B signals, producing two 32-bit results.

For CDMA mode, the integration time is slightly longer. The power read in CDMA mode with a dc input is:

D A power: [ I2 x (X x 4 + 1) + Q2 x (X x 4 + 0) ] x 2−18. Note, one Q sample is missing from the integration.

D B power: [ I2 x (X x 4 + 1) + Q2 x (X x 4 + 1) ] x 2−18

Where X is the integration count.

Table 5. Programming

VARIABLE

DESCRIPTION

pmeter_result_a_lsb(15:0)

Lower 16 bits of the A channel power measurement.

pmeter_result_a_msb (31:16)

Upper 16 bits of the A channel power measurement.

pmeter_result_b_lsb (15:0)

Lower 16 bits of the B channel power measurement result. Only available in CDMA mode.

pmeter_integration_duc(12:0)

Integration time = 4 x pmeter_integration_duc+1.

pmeter_sync_delay_duc(6:0)

Sync delay count in samples.

pmeter_interval_duc(9:0)

Interval time = 64(pmeter_interval_duc+1). Interval time must be greater than (not equal)

integration time.

ssel_pmeter(2:0)

Sync source options.

pmeter_sync_disable

Turns off sync to the channel’s power meter

3.1.5 Transmit Filter Chain

GC5316 transmit filtering is performed in three stages:

D Interpolate by two pulse-shape filtering using the programmable FIR filter (PFIR)

D Interpolate by two compensation filtering using the programmable compensating FIR filter (CFIR)

D High-rate interpolation (4 to 32) using the six stage cascade-integrate comb filter (CIC)

Figure 27. DUC Filter Chain

The purpose of the transmit filter chain is to interpolate the input signal data up to the mixer clock rate, nominally

122.88 MHz. The following table provides two examples of how the interpolation can be allocated among the three

different filters for both CDMA and UMTS.

Table 6. Example UMTS and CDMA2000 DUC Transmit Modes

INPUT RATE

RATE

PFIR

INTERPOLATION

CFIR

INTERPOLATION

CIC

INTERPOLATION

OVERALL

INTERPOLATION

CDMA

1.2288 MSPS

100

UMTS

3.84 MSPS

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