GC5316 datasheet(6/75 Pages) TI

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GC5316

SLWS154A − JANUARY 2004 − REVISED MARCH 2004

www.ti.com

Resampler Decimate by 2

LPF

12 tap

adcclk

rxclk

bus b (or d)

busa(or c)

@ rxclk/2

rxin_a (or c)

@ adcclk

rx_distribution

Figure 4. Resampler Decimate by 2 Mode

The decimate by 2 mode permits input data rates up to the rxclk rate (adcclk frequency equals rxclk frequency). This

is useful for processing up to two real inputs at the rxclk rate and extracting more than 12 CDMA signals. A 12-tap

low-pass decimation filter with programmable 18-bit coefficients removes alias images that would fold into the

passband prior to decimation. Table 3 shows the performance of filters designed for various bandwidths when the

resampler is decimating by 2. Table 3 also shows the resulting passband frequencies assuming the input data rate

is 122.88 MHz. Each horizontal row is a unique 12-tap filter which is available on the web.

Table 3. Resampler Filter Performance in the Decimate by 2 Mode

GENERAL APPLICATION

EXAMPLE APPLICATION

adclk: 122.88 MHz

PASSBAND

RIPPLE

STOPBAND

BANDWIDTH

F LOWER

F CENTER

F UPPER

of clk

MHz

0.06

−109.8

14.7

23.3

30.72

38.1

0.07

−98.8

17.2

22.1

30.72

39.3

0.08

−93.4

19.7

20.9

30.72

40.6

0.09

0.01

−89.2

22.1

19.7

30.72

41.8

0.1

0.02

−81.5

24.6

18.4

30.72

0.11

0.05

−76.8

17.2

30.72

44.2

0.12

0.09

−71.4

29.5

30.72

45.5

0.13

0.16

−66.5

31.9

14.7

30.72

46.7

0.14

0.28

−61.8

34.4

13.5

30.72

47.9

The output of this processing block is complex at rxclk/2 and goes through the selector to drive the rx_distribution

bus. I data for channel rxin_a is routed to a selector driving DDC bus 1, the Q data is input to a selector driving DDC

bus 0. I data for channel rxin_c is routed to a selector driving DDC bus 3, the Q data is input to a selector driving DDC

bus 2.

Table 4. Programming

VARIABLE

DESCRIPTION

resampler_ena

When asserted, turns on the resamplers on input ports rxin_a and rxin_c.

resampler_decim

1 = decimate by 1.5x, 0 = decimate by 2x

rate_sel

This selects the FIFO output rate when adc_fifo_bypass = 0. When using the resampler, this value should be

programmed to a 0. When set to 0, the FIFO output is clocked by rxclk (gated if resampler is on and decimating by

1.5). When set to 1, the FIFO output rate is 1/2 of rxclk rate. When set to 2, the FIFO output rate is 1/4 of rxclk rate,

and when set to 3, the FIFO output is at 1/8 of rxclk rate. e.g.: With rxclk 122.88MHz, set rate_sel to 0, 1, 2, or 3

respectively for adcclk 122.88, 61.44, 30.72, or 15.36 MHz.

ssel_rxin(2:0)

Synchronizes the rx_distribution bus source and destination and clock generation in each of the DDC blocks.

ssel_resamp(2:0)

Synchronizes the resampler Fs/4 mixer and decimation.

ssel_adc_fifo(2:0)

Synchronizes the FIFO read and write pointers (fifo depth).

remix_only

Set to 0 for complex input data, or to 1 for real data. Set this value to 0 when using the resampler. Note that mixed ral

and complex input is not allowed.

resampler

coefficients

The resample’s 18-bit coefficients are loaded by the software cmd5316. The user must provide a coefficient file with

one integer coefficient per line.

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