GC5316 datasheet(59/75 Pages) TI

59 / 75 page

GC5316

SLWS154A − JANUARY 2004 − REVISED MARCH 2004

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agc_gaina_msb

0100

Upper 3 bits of the CDMA channel A (or

UMTS) gain value.

agc_freeze

0100

Keeps the agc from adapting and only

multiplies the input data by the programmed

gain. Should be asserted when the AGC

algorithm is to be bypassed.

agc_max_cnt

0100

when the agc_output ( input x gain ) is at full

scale for this number of times then the gain

shift value is changed to D3.

agc_gainb_msb

0100

Upper 3 bits of the CDMA channel B gain

value.

agc_clear

0100

Clears the AGC accumulator. Should assert

this when the AGC is in bypass mode.

agc_zero_cnt

0100

When the agc_output ( input x gain) is zero

value for this number of times then the gain

shift value is changed to agc_dzero.

agc_gaina_lsb

0120

4096

This is the lower 16 bits of the total 19 bits of

programmable gain. The gaina value is

always positive with the upper 7 bits being

the integer value and the lower 12 bits being

the fractional. This gain value is used for all

UMTS operations and for channel A data

when in CDMA mode. This holds the lower

four integer bits and the 12 fractional bits.

The upper 3 integer bits are stored in the

agc_gaina_msb variable. A value of

0001000000000000 is unity gain.

agc_gainb_lsb

0120

4096

This is the lower 16 bits of the total 19 bits of

programmable gain. The gainb value is

always positive with the upper 7 bits being

the integer value and the lower 12 bits being

the fractional. This gain value is used for

channel B data when in CDMA mode. This

holds the lower four integer bits and the 12

fractional bits. The upper 3 integer bits are

stored in the agc_gainb_msb variable. A

value of 0001000000000000 is unity gain.

agc_amax

0120

512

The maximum value that gain can be

adjusted up to. The top 7 bits are integer and

bottom the 9 bits are fractional.

agc_amin

0120

512

The minimum value that gain can be

adjusted down to. The top 7 bits are integer

and the bottom 9 bits are fractional.

pser_recv_fsinvl

0120

Receive serial interface frame sync interval

in bit clocks.

pser_recv_bits

0120

Number of output bits per sample−1; for 18

bits, this is set to {10001}.

pser_recv_clkdiv

0120

Receive serial interface clock divider rate−1;

0 is full rate and 15 divides the clock by 16.

For example, to run the receive serial

interface at 1/4 the receive clock, set

pser_recv_clkdiv(3:0) = 0011.

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