GC5316 datasheet(4/75 Pages) TI

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GC5316

SLWS154A − JANUARY 2004 − REVISED MARCH 2004

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2.1

Receive Input Interface

FIFO

Resam pler

Block

Select

FIFO

Bypass

Upper 16 of 18

Test & Noise

Generator

Test & Noise

Generator

Resam pler

Block

Select

FIFO

Bypass

Upper 16 of 18

Test & Noise

Generator

Test & N oise

Generator

bus 0

bus 1

bus 2

bus 3

rxin_a

rxin_b

rxin_c

rxin_d

Select

resampler_ena

Special 92.16 MSPS input rate

mode

Figure 2. Receive Input Interface

The four ports support four independent real input signals or two complex. Complex signal data is input with I data

driving one input port and Q data driving another. This means that there are only two signal data ports available when

in complex input mode. The mapping of I and Q data onto the four input ports is programmable.

2.1.1 Test and Noise Generator and FIFO

Incoming data first enters the test and noise generator block. This block can either pass the data through, replace

the input data with a pattern generated internally (useful in test), or can add noise to the input at a user programmable

level.

Most applications pass data through this block unchanged by clearing slf_tst_ena, rduz_sens_ena, and tst_on.

Test sequences are useful for board bring-up or for power-on self-test. Board bring-up and self-test procedures and

configuration files are available on the web. Self-test will be described in greater detail in a later section. Suffice to

say here that the receive data input is replaced by pseudo-random patterns at this point in the processing chain.

A few applications that require receiver desensitization which is done by adding digital noise to the input. The same

pseudo-random sequence generator is used as a noise source. Nz_pwr_mask is used to select which input data bits

get noise added to them. In this way the user has control over the noise power introduced in receiver desensitization.

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