RX113 datasheet(2/131 Pages) RENESAS

2 / 131 page

R01DS0216EJ0120 Rev.1.20

Page 2 of 131

Sep 07, 2020

RX113 Group

1. Overview

Overview

1.1

Outline of Specifications

Table 1.1 lists the specifications, and Table 1.2 gives a comparison of the functions of the products in different

packages.

Table 1.1 is for products with the greatest number of functions, so the number of peripheral modules and channels will

differ in accordance with the package type. For details, see Table 1.2, Comparison of Functions for Different

Packages.

Table 1.1

Outline of Specifications (1/3)

Classification

Module/Function

Description

CPU

• Maximum operating frequency: 32 MHz

• 32-bit RX CPU

• Minimum instruction execution time: One instruction per clock cycle

• Address space: 4-Gbyte linear

• Register set

General purpose: Sixteen 32-bit registers

Control: Eight 32-bit registers

Accumulator: One 64-bit register

• Basic instructions: 73

• DSP instructions: 9

• Addressing modes: 10

• Data arrangement

Instructions: Little endian

Data: Selectable as little endian or big endian

• On-chip 32-bit multiplier: 32-bit × 32-bit → 64-bit

• On-chip divider: 32-bit ÷ 32-bit → 32 bits

• Barrel shifter: 32 bits

Memory

ROM

• Capacity: 128 K/256 K/384 K/512 Kbytes

• 32 MHz, no-wait memory access

• Programming/erasing method:

Serial programming (asynchronous serial communication/USB communication), self-programming

RAM

• Capacity: 32 K/64 Kbytes

• 32 MHz, no-wait memory access

E2 DataFlash

• Capacity: 8 Kbytes

• Number of erase/write cycles: 1,000,000 (typ)

MCU operating mode

Single-chip mode

Clock

Clock generation circuit

• Main clock oscillator, sub-clock oscillator, low-speed on-chip oscillator, high-speed on-chip oscillator,

PLL frequency synthesizer, USB-dedicated PLL frequency synthesizer, and IWDT-dedicated on-chip

oscillator

• Oscillation stop detection: Available

• Clock frequency accuracy measurement circuit (CAC)

• Independent settings for the system clock (ICLK), peripheral module clock (PCLK), and FlashIF clock

(FCLK)

The CPU and system sections such as other bus masters run in synchronization with the system

clock (ICLK): 32 MHz (at max.)

Peripheral modules run in synchronization with the PCLK: 32 MHz (at max.)

The flash peripheral circuit runs in synchronization with the FCLK: 32 MHz (at max.)

• The ICLK frequency can only be set to FCLK, PCLKB, or PCLKD multiplied by n (n: 1, 2, 4, 8, 16, 32,

64).

Resets

RES# pin reset, power-on reset, voltage monitoring reset, independent watchdog timer reset, and

software reset

Voltage detection

Voltage detection circuit

(LVDAa)

• When the voltage on VCC falls below the voltage detection level, an internal reset or internal interrupt

is generated.

Voltage detection circuit 1 is capable of selecting the detection voltage from 10 levels

Voltage detection circuit 2 is capable of selecting the detection voltage from 4 levels

Low power

consumption

Low power consumption

functions

• Module stop function

• Three low power consumption modes

Sleep mode, deep sleep mode, and software standby mode

Function for lower operating

power consumption

• Operating power control modes

High-speed operating mode, middle-speed operating mode, and low-speed operating mode

Interrupt

Interrupt controller (ICUb)

• Interrupt vectors: 120

• External interrupts: 9 (NMI, IRQ0 to IRQ7 pins)

• Non-maskable interrupts: 4 (NMI pin, voltage monitoring 1 interrupt, voltage monitoring 2 interrupt,

and IWDT interrupt)

• 16 levels specifiable for the order of priority

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