RX113 datasheet(29/131 Pages) RENESAS

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R01DS0216EJ0120 Rev.1.20

Page 29 of 131

Sep 07, 2020

RX113 Group

4. I/O Registers

• Longword-size I/O registers

MOV.L #SFR_ADDR, R1

MOV.L #SFR_DATA, [R1]

CMP

[R1].L, R1

;; Next process

When executing an instruction after writing to multiple registers, only read the last I/O register written to and execute the

instruction using that value; it is not necessary to execute the instruction using the values written to all the registers.

(3)

Number of cycles necessary for accessing I/O registers

See Table 4.1 for details on the number of clock cycles necessary for accessing I/O registers.

The number of access cycles to I/O registers is obtained by following equation.*1

Number of access cycles to I/O registers = Number of bus cycles for internal main bus 1 +

Number of divided clock synchronization cycles +

Number of bus cycles for internal peripheral buses 1 to 6

The number of bus cycles of internal peripheral buses 1 to 6 differs according to the register to be accessed.

When peripheral functions connected to internal peripheral buses 2 to 6 or registers for the external bus control unit

(except for bus error related registers) are accessed, the number of divided clock synchronization cycles is added.

The number of divided clock synchronization cycles differs depending on the frequency ratio between ICLK and PCLK

(or FCLK) or bus access timing.

In the peripheral function unit, when the frequency ratio of ICLK is equal to or greater than that of PCLK (or FCLK), the

sum of the number of bus cycles for internal main bus 1 and the number of the divided clock synchronization cycles will

be one cycle of PCLK (or FCLK) at a maximum. Therefore, one PCLK (or FCLK) has been added to the number of

access cycles shown in Table 4.1.

When the frequency ratio of ICLK is lower than that of PCLK (or FCLK), the subsequent bus access is started from the

ICLK cycle following the completion of the access to the peripheral functions. Therefore, the access cycles are described

on an ICLK basis.

Note 1. This applies to the number of cycles when the access from the CPU does not conflict with the bus access from

the different bus master (DTC).

(4)

Notes on sleep mode and mode transitions

During sleep mode or mode transitions, do not write to the system control related registers (indicated by ‘SYSTEM’ in

the Module Symbol column in Table 4.1, List of I/O Registers (Address Order)).

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