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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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RX113 датащи(PDF) 89 Page - Renesas Technology Corp |
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RX113 датащи(HTML) 89 Page - Renesas Technology Corp |
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89 / 131 page  R01DS0216EJ0120 Rev.1.20 Page 89 of 131 Sep 07, 2020 RX113 Group 5. Electrical Characteristics Note: tPcyc: PCLK cycle Note 1. This applies when the SMR.CKS[1:0] bits = 00b and the SNFR.NFCS[2:0] bits = 010b while the SNFR.NFE bit = 1 and the digital filter is enabled. Table 5.34 Timing of On-Chip Peripheral Modules (5) Conditions: 2.7 V ≤ VCC = VCC_USB ≤ 3.6 V, 2.7 V ≤ AVCC0 ≤ 3.6 V, VSS = AVSS0 = VSS_USB = 0 V, fPCLKB ≤ 32 MHz, Ta = –40 to +105°C Item Symbol Min. Max. Unit Test Conditions Simple I2C (Standard mode) SDA0 input rise time tSr — 1000 ns Figure 5.49 SDA0 input fall time tSf — 300 ns SDA0 input spike pulse removal time tSP 04 × tpcyc*1 ns Data input setup time tSDAS 250 — ns Data input hold time tSDAH 0— ns SCL0, SDA0 capacitive load Cb — 400 pF Simple I2C (Fast mode) SCL0, SDA0 input rise time tSr — 300 ns Figure 5.49 SCL0, SDA0 input fall time tSf — 300 ns SCL0, SDA0 input spike pulse removal time tSP 04 × tpcyc*1 ns Data input setup time tSDAS 100 — ns Data input hold time tSDAH 0— ns SCL0, SDA0 capacitive load Cb — 400 pF Table 5.35 Timing of On-Chip Peripheral Modules (6) Conditions: 1.8 V ≤ VCC = VCC_USB ≤ 3.6 V, 1.8 V ≤ AVCC0 ≤ 3.6 V, VSS = AVSS0 = VSS_USB = 0 V, fPCLKB ≤ 32 MHz, Ta = –40 to +105°C Item Symbol Min. Max. Unit Test Conditions SSI AUDIO_MCLK input frequency 2.7 V or above tAUDIO 125 MHz 1.8 V or above 1 4 Output clock cycle tO 250 — ns Figure 5.50 Input clock cycle tI 250 — ns Clock high pulse width tHC 0.4 0.6 to, ti Clock low pulse width tLC 0.4 0.6 to, ti Clock rise time tRC —20 ns Data delay time 2.7 V or above tDTR — 65 ns Figure 5.51 Figure 5.52 1.8 V or above — 105 Setup time 2.7 V or above tSR 65 — ns 1.8 V or above 90 — Hold time tHTR 40 — ns WS changing edge SSIDATA output delay tDTRW — 105 ns Figure 5.53 |
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