RX113 datasheet(3/131 Pages) RENESAS

3 / 131 page

R01DS0216EJ0120 Rev.1.20

Page 3 of 131

Sep 07, 2020

RX113 Group

1. Overview

DMA

Data transfer controller

(DTCa)

• Transfer modes: Normal transfer, repeat transfer, and block transfer

• Activation sources: Interrupts

• Chain transfer function

I/O ports

General I/O ports

100-pin/64-pin

• I/O: 82/46

• Input: 1/1

• Pull-up resistors: 71/41

• Open-drain outputs: 60/34

• 5-V tolerance: 4/4

Event link controller (ELC)

• Event signals of 44 types can be directly connected to the module

• Operations of timer modules are selectable at event input

• Capable of event link operation for port B

Multi-function pin controller (MPC)

Capable of selecting the input/output function from multiple pins

Timers

Multi-function timer pulse

unit 2 (MTU2a)

• (16 bits × 6 channels) × 1 unit

• Time bases for the six 16-bit timer channels can be provided via up to 16 pulse-input/output lines and

three pulse-input lines

• Select from among eight or seven counter-input clock signals for each channel (PCLK/1, PCLK/4,

PCLK/16, PCLK/64, PCLK/256, PCLK/1024, MTCLKA, MTCLKB, MTCLKC, MTCLKD) other than

channel 5, for which only four signals are available.

• Input capture function

• 21 output compare/input capture registers

• Pulse output mode

• Complementary PWM output mode

• Reset synchronous PWM mode

• Phase-counting mode

• Capable of generating conversion start triggers for the A/D converter

Port output enable 2

(POE2a)

Controls the high-impedance state of the MTU’s waveform output pins

Compare match timer

(CMT)

• (16 bits × 2 channels) × 2 units

• Select from among four clock signals (PCLK/8, PCLK/32, PCLK/128, PCLK/512)

Independent watchdog

timer (IWDTa)

• 14 bits × 1 channel

• Count clock: Dedicated low-speed on-chip oscillator for the IWDT

Frequency divided by 1, 16, 32, 64, 128, or 256

Realtime clock (RTCA)

• Clock source: Sub-clock

• Calendar count mode or binary count mode selectable

• Interrupts: Alarm interrupt, periodic interrupt, and carry interrupt

Low power timer (LPT)

• 16 bits × 1 channel

• Clock source: Sub-clock, Dedicated low-speed on-chip oscillator for the IWDT

Frequency divided by 2, 4, 8, 16, or 32

8-bit timer (TMR)

• (8 bits × 2 channels) × 2 units

• Seven internal clocks (PCLK/1, PCLK/2, PCLK/8, PCLK/32, PCLK/64, PCLK/1024, and PCLK/8192)

and an external clock can be selected

• Pulse output and PWM output with any duty cycle are available

• Two channels can be cascaded and used as a 16-bit timer

Communication

functions

Serial communications

interfaces (SCIe, SCIf)

• 8 channels (channel 0, 1, 2, 5, 6, 8, and 9: SCIe, channel 12: SCIf)

• Serial communications modes: Asynchronous, clock synchronous, and smart card interface

• On-chip baud rate generator allows selection of the desired bit rate

• Choice of LSB-first or MSB-first transfer

• Average transfer rate clock can be input from MTU2 timers

• Simple I2C

• Simple SPI

• Master/slave mode supported (SCIf only)

• Start frame and information frame are included (SCIf only)

• Start-bit detection in asynchronous mode: Low level or falling edge is selectable

IrDA interface (IRDA)

• 1 channel (SCI5 used)

• Supports encoding/decoding of waveforms conforming to IrDA standard 1.0

I2C bus interface (RIIC)

• 1 channel

• Communications formats:

I2C bus format/SMBus format

• Master mode or slave mode selectable

• Supports fast mode

Table 1.1

Outline of Specifications (2/3)

Classification

Module/Function

Description

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