| поискавой системы для электроныых деталей |
|
LTC6906 датащи(PDF) 21 Page - Analog Devices |
|
|
|||||||||||||||||||||||||||||
LTC6906 датащи(HTML) 21 Page - Analog Devices |
|
21 / 28 page ![]() LTC6994-1/LTC6994-2 21 Rev. C For more information www.analog.com 699412 F16 LTC6994 IN GND SET OUT V+ DIV C1 0.1µF R1 R2 RSET V+ V+ DIV SET OUT GND IN C1 R1 R2 V+ RSET DCB PACKAGE IN GND SET OUT V+ DIV R2 V+ RSET TSOT-23 PACKAGE R1 C1 APPLICATIONS INFORMATION Figure 16. Supply Bypassing and PCB Layout Supply Bypassing and PCB Layout Guidelines TheLTC6994isanaccuratemonostablemultivibratorwhen used in the appropriate manner. The part is simple to use and by following a few rules, the expected performance is easily achieved. Adequate supply bypassing and proper PCB layout are important to ensure this. Figure 16 shows example PCB layouts for both the SOT-23 and DCB packages using 0603 sized passive components. The layouts assume a two layer board with a ground plane layer beneath and around the LTC6994. These layouts are a guide and need not be followed exactly. 1. Connect the bypass capacitor, C1, directly to the V+ and GND pins using a low inductance path. The connection from C1 to the V+ pin is easily done directly on the top layer. For the DCB package, C1’s connection to GND is also simply done on the top layer. For the SOT-23, OUT can be routed through the C1 pads to allow a good C1 GND connection. If the PCB design rules do not allow that,C1’sGNDconnectioncanbeaccomplishedthrough multiple vias to the ground plane. Multiple vias for both the GND pin connection to the ground plane and the C1 connection to the ground plane are recommended to minimize the inductance. Capacitor C1 should be a 0.1µF ceramic capacitor. 2. Place all passive components on the top side of the board. This minimizes trace inductance. 3. Place RSET as close as possible to the SET pin and make adirect,shortconnection.TheSETpinisacurrentsum- ming node and currents injected into this pin directly modulate the output delay. Having a short connection minimizes the exposure to signal pickup. 4. Connect RSET directly to the GND pin. Using a long path or vias to the ground plane will not have a significant affect on accuracy, but a direct, short connection is recommended and easy to apply. 5. Use a ground trace to shield the SET pin. This provides another layer of protection from radiated signals. 6. Place R1 and R2 close to the DIV pin. A direct, short connection to the DIV pin minimizes the external signal coupling. |
|
ссылки URL |
| Вашему бизинису помогли Аллдатащит? [ DONATE ] |
Что такое Аллдатащит | реклама | контакт | Конфиденциальность | Ссылка на техническое описание | обмен ссыками | поиск по производителю All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |