LTC6906 datasheet(17/28 Pages) AD

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LTC6994-1/LTC6994-2

Rev. C

For more information www.analog.com

APPLICATIONS INFORMATION

Basic Operation

The simplest and most accurate method to program the

LTC6994 is to use a single resistor, RSET, between the SET

and GND pins. The design procedure is a 3-step process.

Alternatively, Linear Technology offers the easy-to-use

TimerBlox Designer tool to quickly design any LTC6994

based circuit. Use the free TimerBlox LTC6994: Delay

Web-Based Design Tool.

Step 1: Select the LTC6994 Version and POL Bit

Setting.

Choose LTC6994-1 to delay one (rising or falling) input

transition. The POL bit then defines which edge is to be

delayed. POL = 0 delays rising edges. POL = 1 delays

falling edges.

Choose LTC6994-2 to delay rising and falling edges. Set

POL = 0 for normal operation, or POL = 1 to invert the

output.

Step 2: Select the NDIV Frequency Divider Value.

As explained earlier, the voltage on the DIV pin sets the

DIVCODE which determines both the POL bit and the

NDIV value. For a given delay time (tDELAY), NDIV should

be selected to be within the following range:

tDELAY

16µs

≤ NDIV ≤

tDELAY

1µs

(1)

To minimize supply current, choose the lowest NDIV value.

However,insomecasesahighervalueforNDIVwillprovide

better accuracy (see Electrical Characteristics).

Table 1 can also be used to select the appropriate NDIV

values for the desired tDELAY.

With POL already chosen, this completes the selection of

DIVCODE. Use Table 1 to select the proper resistor divider

or VDIV/V+ ratio to apply to the DIV pin.

Step 3: Calculate and Select RSET.

The final step is to calculate the correct value for RSET

using the following equation:

RSET =

50k

1µs

•

tDELAY

NDIV

(2)

Select the standard resistor value closest to the calculated

value.

Example: Design a circuit to delay falling edges by

tDELAY = 100µs with minimum power consumption.

Step 1: Select the LTC6994 Version and POL Bit

Setting.

To delay negative transitions, choose the LTC6994-1 with

POL = 1.

Step 2: Select the NDIV Frequency Divider Value.

Choose an NDIV value that meets the requirements of

Equation (1), using tDELAY = 100µs:

6.25 ≤ NDIV ≤ 100

Potential settings for NDIV include 8 and 64. NDIV = 8 is

the best choice, as it minimizes supply current by us-

ing a large RSET resistor. POL = 1 and NDIV = 8 requires

DIVCODE = 14. Using Table 1, choose R1 = 102k and R2

= 976k values to program DIVCODE = 14.

Step 3: Select RSET.

Calculate the correct value for RSET using Equation (2).

RSET =

50k

1µs

•

100µs

= 625k

Since 625k is not available as a standard 1% resistor,

substitute 619k if a –0.97% shift in tDELAY is acceptable.

Otherwise, select a parallel or series pair of resistors such

as 309k and 316k to attain a more precise resistance.

The completed design is shown in Figure 9.

Figure 9. 100µs Negative-Edge Delay

LTC6994-1

GND

SET

OUT

V+

DIV

102k

0.1µF

DIVCODE = 14

699412 F09

2.25V TO 5.5V

976k

RSET

625k

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