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LTC6906 датащи(PDF) 20 Page - Analog Devices

номер детали LTC6906
подробное описание детали  TimerBlox: Delay Block/ Debouncer
PDF  28 Pages
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производитель  AD [Analog Devices]
домашняя страница  http://www.analog.com
Logo AD - Analog Devices

LTC6906 датащи(HTML) 20 Page - Analog Devices

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LTC6994-1/LTC6994-2
20
Rev. C
For more information www.analog.com
Power Supply Current
The Electrical Characteristics table specifies the supply
current while the part is idle (waiting for an input transi-
tion). IS(IDLE) varies with the programmed tDELAY and the
supply voltage, as described by the equations in Table 2,
valid for both the LTC6994-1 and LTC6994-2.
Table 2. Approximate Idle Supply Current Equations
CONDITION
TYPICAL IS(IDLE)
NDIV ≤ 64
V + • NDIV • 7pF + 4pF
(
)
tDELAY
+
V +
500kΩ
+ 2.2 •ISET + 50µA
NDIV ≥ 512
V + •NDIV • 7pF
tDELAY
+
V +
500kΩ
+ 1.8 •ISET + 50µA
When an input transition starts the delay timing circuity,
the instantaneous supply current increases to IS(ACTIVE).
IS(ACTIVE) = IS(IDLE) + ∆IS(ACTIVE)
APPLICATIONS INFORMATION
∆IS(ACTIVE)canbeestimatedusingtheequationsinTable 3,
assuming a periodic input with frequency fIN. The equa-
tions assume the input pulse width is greater than tDELAY;
otherwise, the output will not transition (and the increase
in supply current will be less).
Table 3. Active Increase in Supply Current
CONDITION
DEVICE
TYPICAL ∆IS(ACTIVE)*
NDIV ≤ 64
LTC6994-1
fIN • V+ • (NDIV • 5pF + 18pF + CLOAD)
LTC6994-2
fIN • V+ • (NDIV • 10pF + 22pF + CLOAD)
NDIV ≥ 512 Either Version
fIN • V+ • CLOAD
*Ignoring resistive loads (assumes RLOAD = ∞)
Figures 14 and 15 show how the supply current increases
from IS(IDLE) as the input frequency increases. At higher
NDIV settings, the increase in active current is smaller.
fIN • tDELAY
“IDLE”
150
200
250
0.8
699412 F14
100
50
0
0.2
0.4
0.6
1.0
÷1, RSET = 50k
÷8, RSET = 50k
÷1, RSET = 100k
÷1, RSET = 800k
V+ = 3.3V
INPUT PULSE WIDTH = 1.1 • tDELAY
CLOAD = 5pF
RLOAD = ∞
fIN • tDELAY
“IDLE”
150
200
250
0.4
699412 F15
100
50
0
0.1
0.2
0.3
0.5
÷1, RSET = 50k
÷8, RSET = 50k
÷1, RSET = 100k
÷1, RSET = 800k
V+ = 3.3V
fIN < 1/(2 • tDELAY) TO ALLOW RISING AND
FALLING DELAYS TO REACH THE OUTPUT
CLOAD = 5pF
RLOAD = ∞
Figure 14. IS(ACTIVE) vs Input Frequency, LTC6994-1
Figure 15. IS(ACTIVE) vs Input Frequency, LTC6994-2



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