LTC6906 datasheet(13/28 Pages) AD

13 / 28 page

LTC6994-1/LTC6994-2

Rev. C

For more information www.analog.com

OPERATION

Table 1. DIVCODE Programming

DIVCODE

POL

NDIV

Recommended tDELAY

R1 (k)

R2 (k)

VDIV/V+

1µs to 16µs

Open

Short

≤ 0.03125 ±0.015

8µs to 128µs

976

102

0.09375 ±0.015

64µs to 1.024ms

976

182

0.15625 ±0.015

512

512µs to 8.192ms

1000

280

0.21875 ±0.015

4,096

4.096ms to 65.54ms

1000

392

0.28125 ±0.015

32,768

32.77ms to 524.3ms

1000

523

0.34375 ±0.015

262,144

262.1ms to 4.194sec

1000

681

0.40625 ±0.015

2,097,152

2.097sec to 33.55sec

1000

887

0.46875 ±0.015

2,097,152

2.097sec to 33.55sec

887

1000

0.53125 ±0.015

262,144

262.1ms to 4.194sec

681

1000

0.59375 ±0.015

32,768

32.77ms to 524.3ms

523

1000

0.65625 ±0.015

4,096

4.096ms to 65.54ms

392

1000

0.71875 ±0.015

512

512µs to 8.192ms

280

1000

0.78125 ±0.015

64µs to 1.024ms

182

976

0.84375 ±0.015

8µs to 128µs

102

976

0.90625 ±0.015

1µs to 16µs

Short

Open

≥ 0.96875 ±0.015

Figure 2. Delay Range and POL Bit vs DIVCODE

If the voltage is generated by other means (i.e., the output

of a DAC) it must track the V+ supply voltage. The last

column in Table 1 shows the ideal ratio of VDIV to the

supply voltage, which can also be calculated as:

VDIV

V +

DIVCODE + 0.5

± 1.5%

Forexample,ifthesupplyis3.3VandthedesiredDIVCODE

is 4, VDIV = 0.281 • 3.3V = 928mV ± 50mV.

Figure 2 illustrates the information in Table 1, showing

that NDIV is symmetric around the DIVCODE midpoint.

0.5•V+

699412 F02

1000

10000

100

0.001

0.1

0.01

INCREASING VDIV

V+

POL BIT = 0

POL BIT = 1

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