AS9C25512M2018L

AS9C25256M2018L

9/24/04, v.1.2

Alliance Semiconductor

P. 8 of 30

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Notes:

1. L = low, H = high

2. CE0 = L, CE1 = H (Chip in Select mode)

3. R/W = H for a Read operation, R/W = L for a Write operation

4. Byte 1 - DQ[17:9], Byte 0 - DQ[8:0]

5. More than one byte enable may be simultaneously asserted

Notes:

1. L = low, H = high, X = don't care

2. CE is an internal signal. CE = H implies 'Chip is Deselected' (CE0 = H or CE1 =L), CE = L implies 'Chip is Selected' (CE0 = L and CE1 =H)

4. Snooze de-asserted (ZZ=L)

5. True in flow-through mode. For Pipeline mode there will be a 1 cycle latency [refer timing diagrams]

6. For a write command issued before the completion of a read command, OE must be HIGH before the input data setup time and held HIGH throughout the input data hold time.

7. All DQs are tristated on power-up

8. OE should be asserted (OE = L) (Refer Read timing waveform)

9. In pipeline mode the DQs are HighZ-ed in the same cycle if R/W=L

Notes:

1. L = low, H = high, X = don't care

4. The 'Mirror register' used for the Repeat operation is loaded with External address during every valid ADS access. “Am” refers to the mirror register content.

5. Clock to the counter is disabled during Snooze mode (True for both ports).

6. The counter and the mirror registers are not initialized on Power-up (refer Counter description).

BE1

BE0

CLK

Mode

H

H

L to H

All Bytes Deselected - NOP

H

L

L to H

Read or Write Byte 0

L

H

L to H

Read or Write Byte 1

R/W

CLK

Operation

H

X

X

L to H

Chip Deselect

L

X

H

L to H

Byte Deselect

L

L

L

L to H

Byte Write

L

H

L

L to H

Byte Read

CLK

External

Address

Previous

Address

Accessed

Mirror

Register

Address

Accessed

Operation

L to H

L

X

H

An

X

An

An

L to H

H

L

H

X

An

Am

An + 1

Increment

L to H

H

H

H

X

An

Am

An

Hold

L to H

X

X

L

X

X

Am

Am

Repeat