AS9C25512M2018L

AS9C25256M2018L

9/24/04, v.1.2

Alliance Semiconductor

P. 20 of 30

®

Depth and Width expansion

AS9C25512M2018L/AS9C25256M2018L has two chipselects (one active high and other active low) for simple depth expansion. This

permits easy upgrade from 512/256K depth to 1M/512K depth without extra logic. Two such parts can also be combined to obtain an

expanded width of 36 bits or wider.

Notes:

1. A<0:18> for AS9C25512M2018L, A<0:17> for AS9C25256M2018L

2. A<0:19> for AS9C25512M2018L, A<0:18> for AS9C25256M2018L

3. A<19> for AS9C25512M2018L, A<18> for AS9C25256M2018L

Notes:

2. A<0:18> for AS9C25512M2018L, A<0:17> for AS9C25256M2018L

3. A<19> for AS9C25512M2018L, A<18> for AS9C25256M2018L

4. Refer to the above block diagram for the assumed setup.

5. One Bank is assumed to have two AS9C25512M2018L/AS9C25256M2018Ls combined to have an expanded width of 36 bits. Two such Banks are used for depth expansion.

6. All BEn's = L, Counter set in “Load” mode (ADS = L, INC = X, RPT = H), OE =L.

RPT

INC

ADS

OE

BE<0:1>

R/W

CLK

CE1

CE0

RPT

INC

ADS

OE

BE<0:1>

R/W

CLK

CE1

CE0

Clock

Clock

Data

Address

Controller

Microprocessor

BANK 1

BANK 0

512/256Kx18

DPSRAM

DPSRAM

DQ<0:35>

512/256Kx18

CLK

R/W

DATA OUT [0:35]

[Pipeline Mode]

(BANK 0)

(BANK 1)

DATA OUT [0:35]

[Flow-through Mode]

[Pipeline Mode]

DATA OUT [0:35]

(BANK 0)

DATA OUT [0:35]

[Flow-through Mode]

(BANK 1)

A1

A2

A3

A4

A5

A6

A7

A8

Q1

Q2

Q4

Q3

Q4

Q1

Q2

Q3

Q5

Q6

Read

(Bank0)

(Bank0)

Read

(Bank1)

Read

Read

Read

Read

(Bank0)

(Bank1)

(Bank1)

Read

(Bank0)

Q5

Q6

Don’t care

Undefined