AS9C25512M2018L

AS9C25256M2018L

9/24/04, v.1.2

Alliance Semiconductor

P. 13 of 30

®

Notes:

1. Both Flow-through and Pipeline Outputs indicated. A particular port is configured in Flow-through mode if PL/FT for that port is driven low,

and in Pipeline mode if PL/FT is driven high or left unconnected.

3. CE is an internal signal.CE = H implies 'Chip is Deselected' (CE0 = H or CE1 =L), CE = L implies 'Chip is Selected' (CE0 = L and CE1 =H).

Timings indicated for CE hold good for CE0 and CE1

4. BEn refers to any one of the 2 byte controls [n = 1 or 0] and DATA OUT refers to the corresponding Byte.

5. Counter set in “Load” mode (ADS = L,INC = X,RPT = H).

6. OE is an asynchronous input.

7. All timings are similar for both ports.

8. Read with Byte disabled. Data is not read out.Bus in High-Z condition.

CLK

R/W

[Pipeline Mode]

Q1

A1

A2

A3

A4

A5

A6

A7

A8

A9

A10

A11

A12

A13

Q10

Read

(A1)

Q1

Q2

Q8

Read

(A2)

Dsel

(A4)

Dsel

Read

(A6)

Read

(A7)

Read

(A8)

Dsel

Read

(A10)

Dsel

Read

(A12)

Don’t care

Undefined

Q6

[Pipeline Mode]

Q1

Q10

Q1

Q2

Q8

Q6

[Flow-through Mode]

[Flow-through Mode]

Q12