AS9C25512M2018L

AS9C25256M2018L

9/24/04, v.1.2

Alliance Semiconductor

P. 7 of 30

®

Signal description

Notes:

1. Subscript 'x' represents 'A' for Port A and 'B' for Port B.

Each port can independently operate on either of the VDDQ levels.

4. If unused JTAG inputs may be left unconnected.

5. JTAG, Collision Detection & Interrupt features are not supported in TQFP package.

6. Address A18 is a NC for AS9C25256M2018L.

Signal

I/O Properties

Description

Notes

Port A

Port B

ICLOCK

Clock. Each port has an independent Clock input that can be of different frequencies. All

setup and hold time about the rising edge of the clock.

1

I

SYNC

External Address. Sampled on the rising edge of corresponding port clock

6

SYNC

Bidirectional data pins

ISYNC

Chip enable inputs. Active low and high, respectively. Sampled on the rising edge of

corresponding port clock.

I

SYNC

Read/Write enable. Drive this pin LOW to write to, or HIGH to Read from the memory array.

ISYNC

Byte Enable Inputs. Active low. Asserting these signals enables Read and Write operations to

the corresponding bytes of the memory array. (Refer Byte Control Truth Table)

ISYNC

Address Strobe Enable.Active low. Loads external address onto the counter. (Refer Counter

Control Truth Table)

ISYNC

Address Counter Increment. Active low. Increments the counter value. (Refer Counter Control

Truth Table)

ISYNC

Address Counter Repeat. Active low. Reloads the counter with the previously loaded external

address.(Refer Counter Control Truth Table)

I

ASYNC

I

ASYNC

Snooze Mode Input. Places the device in low power mode. Data is retained. This pin has an

internal pull-down and can be floating.

ISTATIC

Pipeline/Flow-Through Select. When low, enables single register flow-through mode. When

high, enables double register Pipeline mode. This pin has an internal pull-up and can be left

floating to operate in pipeline mode.

ISTATIC

controls on that port. This pin has an internal pull-up and can be left floating to operate in 3.3V

mode.

1,2,3

OSYNC

Interrupt Flag. Used for message passing between two ports. (Refer Interrupt Logic Truth

Table)

5

OSYNC

Collision Alert Flag. Used to indicate collision during simultaneous memory access to the

same location by both the ports (Refer Collision Detection Truth Table)

5

I

POWER

1,2,3

VDD

I

POWER

Power Inputs (To be connected to 2.5V Power supply)

2

VSS

I

GROUND Ground Inputs (To be connected to Ground supply)

TCK

I

CLOCK

(JTAG)

4,5

TDI

I

SYNC

(JTAG)

JTAG Test Data Input. Data on the TDI input will be shifted serially into selected registers.

4,5

TDO

O

SYNC

(JTAG)

JTAG Test Data Output. TDO transitions occur on the falling edge of TCK. TDO is normally

tristated except when the captured data is shifted out of the JTAG TAP.

5

TMS

I

SYNC

(JTAG)

JTAG Test Mode Select Input. It controls the JTAG TAP state machine. State machine

transitions occur on the rising edge of TCK.

4,5

TRST

I

ASYNC

(JTAG)

JTAG Test Reset Input. Asynchronous input used to initialize TAP controller.

4,5