RT1050 datasheet(13/110 Pages) NXP

13 / 110 page

Modules list

i.MX RT1050 Crossover Processors Data Sheet for Industrial Products, Rev. 1.4, 01/2020

NXP Semiconductors

ROMCP

ROM Controller with

Patch

Memories and

Memory Controllers

The ROMCP acts as an interface between the Arm

advanced high-performance bus and the ROM. The

on-chip ROM is only used by the Cortex-M7 core during

boot up. Size of the ROM is 96 KB.

RTC OSC

Real Time Clock

Oscillator

Clock Sources and

Control

The RTC OSC provides the clock source for the

Real-Time Clock module. The RTC OSC module, in

conjunction with an external crystal, generates a 32.678

kHz reference clock for the RTC.

RTWDOG

Watch Dog

Timer Peripherals

The RTWDG module is a high reliability independent

timer that is available for system to use. It provides a

safety feature to ensure software is executing as

planned and the CPU is not stuck in an infinite loop or

executing unintended code. If the WDOG module is not

serviced (refreshed) within a certain period, it resets the

MCU. Windowed refresh mode is supported as well.

SAI1

SAI2

SAI3

Synchronous Audio

Interface

Multimedia

Peripherals

The SAI module provides a synchronous audio

interface (SAI) that supports full duplex serial interfaces

with frame synchronization, such as I2S, AC97, TDM,

and codec/DSP interfaces.

SA-TRNG

Standalone True Random

Number Generator

Security

The SA-TRNG is hardware accelerator that generates

a 512-bit entropy as needed by an entropy consuming

module or by other post processing functions.

SEMC

Smart External Memory

Controller

Memory and

Memory Controller

The SEMC is a multi-standard memory controller

optimized for both high-performance and low pin-count.

It can support multiple external memories in the same

application with shared address and data pins. The

interface supported includes SDRAM, NOR Flash,

SRAM, and NAND Flash, as well as 8080 display

interface.

SJC

System JTAG Controller

System Control

Peripherals

The SJC provides JTAG interface, which complies with

JTAG TAP standards, to internal logic. The i.MX

RT1050 processors use JTAG port for production,

testing, and system debugging. In addition, the SJC

provides BSR (Boundary Scan Register) standard

support, which complies with IEEE 1149.1 and IEEE

1149.6 standards.

The JTAG port is accessible during platform initial

laboratory bring-up, for manufacturing tests and

troubleshooting, as well as for software debugging by

authorized entities. The i.MX RT1050 SJC incorporates

three security modes for protecting against

unauthorized accesses. Modes are selected through

eFUSE configuration.

SNVS

Secure Non-Volatile

Storage

Security

Secure Non-Volatile Storage, including Secure Real

Time Clock, Security State Machine, and Master Key

Control.

Table 2. i.MX RT1050 modules list (continued)

Block Mnemonic

Block Name

Subsystem

Brief Description

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