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RT1050 датащи(PDF) 71 Page - NXP Semiconductors

номер детали RT1050
подробное описание детали  Crossover processors data sheet for industrial products
PDF  110 Pages
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производитель  NXP [NXP Semiconductors]
домашняя страница  http://www.nxp.com
Logo NXP - NXP Semiconductors

RT1050 датащи(HTML) 71 Page - NXP Semiconductors

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Electrical characteristics
i.MX RT1050 Crossover Processors Data Sheet for Industrial Products, Rev. 1.4, 01/2020
NXP Semiconductors
71
4.9.3.3
SDR50/SDR104 AC timing
Figure 45 depicts the timing of SDR50/SDR104, and Table 62 lists the SDR50/SDR104 timing
characteristics.
Figure 45. SDR50/SDR104 timing
Table 62. SDR50/SDR104 interface timing specification
ID
Parameter
Symbols
Min
Max
Unit
Card Input Clock
SD1
Clock Frequency Period
tCLK
5.0
—
ns
SD2
Clock Low Time
tCL
0.46 x tCLK
0.54 x tCLK
ns
SD3
Clock High Time
tCH
0.46 x tCLK
0.54 x tCLK
ns
uSDHC Output/Card Inputs SD_CMD, SDx_DATAx in SDR50 (Reference to CLK)
SD4
uSDHC Output Delay
tOD
–3
1
ns
uSDHC Output/Card Inputs SD_CMD, SDx_DATAx in SDR104 (Reference to CLK)
SD5
uSDHC Output Delay
tOD
–1.6
1
ns
uSDHC Input/Card Outputs SD_CMD, SDx_DATAx in SDR50 (Reference to CLK)
SD6
uSDHC Input Setup Time
tISU
2.5
—
ns
SD7
uSDHC Input Hold Time
tIH
1.5
—
ns
uSDHC Input/Card Outputs SD_CMD, SDx_DATAx in SDR104 (Reference to CLK)1
1Data window in SDR104 mode is variable.
SD8
Card Output Data Window
tODW
0.5 x tCLK
—ns
SCK
4-bit output from uSDHC to card
4-bit input from card to uSDHC
SD8
SD7
SD6
SD4/SD5
SD2
SD3
SD1



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