RT1050 datasheet(2/110 Pages) NXP

2 / 110 page

i.MX RT1050 Crossover Processors Data Sheet for Industrial Products, Rev. 1.4, 01/2020

NXP Semiconductors

i.MX RT1050 introduction

i.MX RT1050 has analog interfaces, such as ADC, ACMP, and TSC.

The i.MX RT1050 is specifically useful for applications such as:

•

Industrial Human Machine Interfaces (HMI)

•

Motor Control

•

Home Appliance

1.1

Features

The i.MX RT1050 processors are based on Arm Cortex-M7 MPCore™ Platform, which has the

following features:

•

Supports single Arm Cortex-M7 MPCore with:

— 32 KB L1 Instruction Cache

— 32 KB L1 Data Cache

— Full featured Floating Point Unit (FPU) with support of the VFPv5 architecture

— Support the Armv7-M Thumb instruction set

•

Integrated MPU, up to 16 individual protection regions

•

Up to 512 KB I-TCM and D-TCM in total

•

Frequency of 528 MHz

•

Cortex M7 CoreSight™ components integration for debug

•

Frequency of the core, as per Table 10, "Operating ranges," on page 20.

The SoC-level memory system consists of the following additional components:

— Boot ROM (96 KB)

— On-chip RAM (512 KB)

– Configurable RAM size up to 512 KB shared with M7 TCM

•

External memory interfaces:

— 8/16-bit SDRAM, up to SDRAM-166

— 8/16-bit SLC NAND FLASH, with ECC handled in software

—SD/eMMC

— SPI NOR/NAND FLASH

— Parallel NOR FLASH with XIP support

— Single/Dual channel Quad SPI FLASH with XIP support

•

Timers and PWMs:

— Two General Programmable Timers (GPT)

– 4-channel generic 32-bit resolution timer

– Each support standard capture and compare operation

— Four Periodical Interrupt Timer (PIT)

– Generic 16-bit resolution timer

– Periodical interrupt generation

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