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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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RT1050 датащи(PDF) 65 Page - NXP Semiconductors |
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RT1050 датащи(HTML) 65 Page - NXP Semiconductors |
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65 / 110 page  Electrical characteristics i.MX RT1050 Crossover Processors Data Sheet for Industrial Products, Rev. 1.4, 01/2020 NXP Semiconductors 65 Figure 39. LPSPI Master mode timing (CPHA = 0) Table 57. LPSPI Master mode timing Number Symbol Description Min. Max. Units Note 1fSCK Frequency of operation — fperiph / 2 Hz 1 1 Absolute maximum frequency of operation (fop) is 30 MHz. The clock driver in the LPSPI module for fperiph must be guaranteed this limit is not exceeded. 2tSCK SCK period 2 x tperiph —ns 2 2 tperiph = 1 / fperiph 3tLead Enable lead time 1 — tperiph — 4tLag Enable lag time 1 — tperiph — 5tWSCK Clock (SCK) high or low time tSCK / 2 - 3 — ns — 6tSU Data setup time (inputs) 10 — ns — 7tHI Data hold time (inputs) 2 — ns — 8tV Data valid (after SCK edge) — 8 ns — 9tHO Data hold time (outputs) 0 — ns — (OUTPUT) 2 8 6 7 MSB IN 2 LSB IN MSB OUT 2 LSB OUT 9 5 5 3 (CPOL=0) 4 SCK SCK (CPOL=1) 2. LSBF = 0. For LSBF = 1, bit order is LSB, bit 1, ..., bit 6, MSB. 1. If configured as an output. PCS 1 (OUTPUT) (OUTPUT) SOUT (OUTPUT) SIN (INPUT) BIT 6 . . . 1 BIT 6 . . . 1 |
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