TLE9461ES datasheet(20/140 Pages) INFINEON

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TLE9461ES

Lite CAN SBC Family

System Features

Datasheet

Rev.1.1

2019-09-27

5.1.1

Device Configuration and SBC Init Mode

The device starts up in SBC Init Mode after crossing the power-on reset threshold VPOR,r (see also

Chapter 12.3) and the watchdog starts with a long open window (tLW) after RSTN is released (High level).

During this power-on phase the following configurations are stored in the device:

• The device behavior regarding a watchdog trigger failure and a VCC1 over voltage condition is determined

by the external circuit on the INTN pin (typ. 47 kΩ pull-up resistor to VCC1, see also below)

• The selection of the normal user mode operation or the SBC Development Mode (watchdog = Off, CAN =

On, VCC2 = On for debugging purposes) is set depending on the voltage level of the TEST pin (see also

Chapter 5.1.7).

5.1.1.1

Device Configuration

The configuration selection selects the SBC behavior due to a watchdog trigger failure and VCC1 overvoltage

detection. Depending on the requirements of the application, two different configurations can be chosen:

- If the VCC1 output shall be switched Off and the device shall go to SBC Fail-Safe Mode in case of a watchdog

failure (1 or 2 fails). To set this configuration (Config 2/4), the INTN pin does not need an external pull-up

resistor.

- If VCC1 should not be switched Off (Config 1/3), the INTN pin needs to have an external pull-up resistor

connected to VCC1 (see application diagram in Chapter 14).

Figure 4 shows the timing diagram of the hardware configuration selection. The hardware configuration is

defined during SBC Init Mode. The INTN pin is internally pulled Low with a weak pull-down resistor during the

reset delay time tRD1, i.e. after VCC1 crosses the reset threshold VRT1 and before the RSTN pin goes High. The

INTN pin is monitored during this time (with a continuous filter time of tCFG_F) and the configuration

(depending on the voltage level at INTN) is stored at the rising edge of RSTN.

Note:

If the POR bit is not cleared, then the internal pull-down resistor at INTN is reactivated every time

RSTN is pulled Low the configuration is updated at the rising edge of RSTN. Therefore it is

recommended to clear the POR bit right after initialization. In case there is no stable signal at INTN,

then the last filtered value is taken. If no filtered value is taken then the default value ‘0’ is taken as

the config select value (= SBC Fail-Safe Mode).

Note:

During device power up, the SPI status bits VCC1_ WARN, VCC1_UV and VS_UV are updated only if

RSTN is released after the reset delay time.

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