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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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TLE9461ES датащи(PDF) 19 Page - Infineon Technologies AG |
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TLE9461ES датащи(HTML) 19 Page - Infineon Technologies AG |
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19 / 140 page  TLE9461ES Lite CAN SBC Family System Features Datasheet 19 Rev.1.1 2019-09-27 5.1 Block Description of State Machine The different SBC operating modes are selected via SPI by setting the respective SBC MODE bits in the register M_S_CTRL. The SBC MODE bits are cleared when going through SBC Restart Mode and thus always show the current SBC mode. Figure 3 State Diagram showing the SBC Operating Modes SBC Init Mode * (Long open window) VCC1 ON VCC2 OFF FOx inact. CAN (3) OFF Wake up event SPI cmd SPI cmd SPI cmd Any SPI command WD trigger First battery connection VCC1 Undervoltage Automatic 1st Watchdog Failure Config 2, 2nd Watchdog Failure, Config 4 VCC1 Short to GND SBC Soft Reset § Reset is released § WD starts with long open window (1) After Fail-Safe Mode entry, the device will stay for at least typ . 1s in this mode (with RO low) after a TSD2 event and min. typ. 100ms after other Fail-Safe Events. Only then the device can leave the mode via a wake-up event. Wake events are stored during this time. (3) For SBC Development Mode CAN/VCC2 are ON in SBC Init Mode and stay ON when going from there to SBC Normal Mode (4) See chapter CAN for detailed behavior in SBC Restart Mode (5) See Chapter5.1.5 and 11.1 for detailed FOx behavior WD config. SBC Normal Mode VCC1 ON VCC2 config. FOx act/inact CAN (3) config. WD config. CP config. SBC Sleep Mode VCC1 OFF VCC2 fixed FOx fixed CAN Wake capable /off WD OFF. CP fixed SBC Stop Mode VCC1 ON VCC2 fixed FOx fixed CAN fixed WD fixed CP fixed SBC Restart Mode (RO pin is asserted) VCC1 ON/ ramping VCC2 OFF FOx(5) active/ fixed CAN (4) woken / OFF WD OFF CP fixed SBC Fail-Safe Mode (1) VCC1 OFF VCC2 OFF FOx (5) active CAN Wake capable WD OFF CP fixed Config.: settings can be changed in this SBC mode ; Fixed: settings stay as defined in SBC Normal Mode TSD2 event, * The SBC Development Mode is a super set of state machine where the WD timer is stopped , CAN & VCC2 behavior differs in SBC Init Mode. Otherwise, there are no differences in behavior . Cyc. W/S OFF SPI enabled Cyc. W/S config. SPI config. Cyc. W/S fixed SPI enabled SPI disabled Cyc. W/S OFF SPI disabled Cyc. W/S OFF SPI disabled CAN, WK, GPIO WK wake-up event OR Release of over temperature TSD2 after tTSD2 VCC1 over voltage Config 2/4 (if VCC_OV_RST set) VCC1 over voltage Config 1/3 (if VCC_OV_RST set) Watchdog Failure: Config 1/3 & 1st WD failure in Config4 Cyc. W/S fixed CP OFF/fixed Bit Locking Mechanism: certain control bits, e.g. the Charge Pump (CP) can be locked and will not change their configuration after a Soft Reset command (stay fixed) SBC Sleep Mode entry without any wake source enabled |
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