TLE9461ES datasheet(18/140 Pages) INFINEON

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TLE9461ES

Lite CAN SBC Family

System Features

Datasheet

Rev.1.1

2019-09-27

System Features

This chapter describes the system features and behavior of the TLE9461ES:

• State machine

• Device configuration

•SBC mode control

• State of supplies and peripherals

• System functions such as Cyclic Sense or Cyclic Wake

• Charge pump output for reverse polarity protection and Kl. 30 load switching

• High-voltage measurement interface

The System Basis Chip (SBC) offers six operating modes:

• SBC Init Mode: Power-up of the device (initial and after a soft reset),

• SBC Normal Mode: The main operating mode of the device,

• SBC Stop Mode: The first-level power saving mode (the main voltage regulator VCC1 remains enabled),

• SBC Sleep Mode: The second-level power saving mode (VCC1 is disabled),

•SBC Restart Mode: An intermediate mode after a wake-up event from SBC Sleep or Fail-Safe Mode or after

a failure (e.g. WD failure, VCC1 under voltage reset) to bring the microcontroller into a defined state via a

reset. Once the failure condition is not present anymore the device will automatically change to SBC

Normal Mode after a delay time (tRD1 or tRD2).

• SBC Fail-Safe Mode: A safe-state mode after critical failures (e.g. WD failure, VCC1 under voltage reset) to

bring the system into a safe state and to ensure a proper restart of the system later on. VCC1 is disabled. It

is a permanent state until either a wake-up event (via CAN, WK/VSENSE or GPIO configured as wake-up)

occurs or the over temperature condition is not present anymore.

A special mode, called SBC Development Mode, is available during software development or debugging of the

system. All above mentioned operating modes can be accessed in this mode. However, the watchdog counter

is stopped and does not need to be triggered. In addition, CAN is set to normal mode and VCC2 is On. This

mode can be accessed by connecting the TEST pin to VCC1 during SBC Init Mode.

The device can be configured via hardware to determine the device behavior after a watchdog trigger failure.

See Chapter 5.1.1 for further information.

The System Basis Chip is controlled via a 16-bit SPI interface. A detailed description can be found in

Chapter 13. The device configuration as well as the diagnosis is handled via the SPI. The SPI mapping of the

TLE9461ES is compatible to other devices of the TLE926x and TLE927x families.

The device offers various supervision features to support functional safety requirements. Please see

Chapter 12 for more information.

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