ASL4501SHN datasheet(13/43 Pages) NXP

13 / 43 page

ASL4501SHN

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 2 — 10 January 2018

13 of 43

NXP Semiconductors

ASL4501SHN

Four-phase boost converter

Note: To obtain the best performance of the internal slope compensation, keep the

settings of the delay between the phases as close to 32 as possible.

8.2.6 Control loop parameter settings

The ASL4501SHN is able to operate with a wide range of external components and offers

a wide range of operating frequencies. To achieve maximum performance for each set of

operation conditions, set the control loop parameters in accordance with the external

components and operating frequency.

Table 10.

Clock divider for Vout1 (address 09h)

Bit

Symbol

Description

Value

Function

7 to 0 Clkdiv1[7:0]

clock divider for phase

logic 1

00h

clock is not divided

...

clock is divided by Clkdiv1[7:0] + 1

FFh

clock is divided by 256

Table 11.

Clock divider for Vout2 (address 0Ah)

Bit

Symbol

Description

Value

Function

7 to 0 Clkdiv2[7:0]

clock divider for phase

logic 2

00h

clock is not divided

...

clock is divided by Clkdiv2[7:0] + 1

FFh

clock is divided by 256

Table 12.

Phase-off time and phase delay of output 1 (address 0Dh)

Bit

Symbol

Description

Value Function

7 to 3 Phdel1[4:0] delay to next

phase of phase

logic 1

phase delay is 1 clock period of the divided clock

...

phase delay is Phdel1[4:0] + 1 clock period of the

divided clock

1Fh

phase delay is 32 clock periods of the divided clock

2 to 0 Phoff1[2:0]

phase-off time

of phase logic 1

phase-off time is 1 clock period of the divided clock

...

phase-off time is Phoff1[2:0] clock period of the

divided clock

phase-off time is 7 clock periods of the divided clock

Table 13.

Phase-off time and phase delay of output 2 (address 0Eh)

Bit

Symbol

Description

Value Function

7 to 3 Phdel2[4:0] delay to next

phase of phase

logic 2

phase delay is 1 clock period of the divided clock

...

phase delay is Phdel2[4:0] + 1 clock period of the

divided clock

1Fh

phase delay is 32 clock periods of the divided clock

2 to 0 Phoff2[2:0]

phase-off time

of phase logic 2

phase-off time is 1 clock period of the divided clock

...

phase-off time is Phoff2[2:0] clock period of the

divided clock

phase-off time is 7 clock periods of the divided clock

ASL4501SHN датащи(PDF) 13 Page - NXP Semiconductors

ASL4501SHN датащи(HTML) 13 Page - NXP Semiconductors

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43

датащи скачать

ссылки URL