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ASL4501SHN датащи(PDF) 35 Page - NXP Semiconductors |
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ASL4501SHN датащи(HTML) 35 Page - NXP Semiconductors |
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35 / 43 page ![]() ASL4501SHN All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2018. All rights reserved. Product data sheet Rev. 2 — 10 January 2018 35 of 43 NXP Semiconductors ASL4501SHN Four-phase boost converter 12. Dynamic characteristics [1] All parameters are guaranteed over the virtual junction temperature range by design. Factory testing uses correlated test conditions to cover the specified temperature and power supply voltage range. Table 46. Dynamic characteristics Minimum and maximum values are specified for the following conditions: VBAT = 5.5 V to 40 V, VEN = 4.5 V to 5.5 V, fosc = 130 MHz to 200 MHz, VCC = 4.5 V to 5.5 V and Tj = 40 C to +175 C[1]. All voltages are defined with respect to ground. Positive currents flow into the IC. Typical values are given at VBAT = 12 V, VEN = 5 V, VCC = 5 V and Tj =25 C unless otherwise specified. Symbol Parameter Conditions Min Typ Max Unit fDCDC DC-to-DC converter frequency 125 - 700 kHz fDCDC(acc) DC-to-DC converter frequency accuracy operating; trimmed 5- +5 % fosc oscillator frequency internal oscillator; untrimmed 130 - 250 MHz target frequency for trimmed operation - 180 - MHz tstartup start-up time EN = HIGH until SPI write access - - 150 s EN = HIGH until SPI read access - - 2000 s Serial peripheral interface timing; pins CSB, SCLK, SDI and SDO fclk(int)/fSPI_CLK internal clock frequency to SPI clock frequency ratio -20 : 1 - 1 tcy(clk) clock cycle time 250 - - ns tSPILEAD SPI enable lead time 50 - - ns tSPILAG SPI enable lag time 50 - - ns tclk(H) clock HIGH time 125 - - ns tclk(L) clock LOW time 125 - - ns tsu(D) data input set-up time 50 - - ns th(D) data input hold time 50 - - ns tv(Q) data output valid time pin SDO; CL = 20 pF - - 130 ns tWH(S) chip select pulse width HIGH 250 - - ns Gate driver tch(g) gate charge time 20 % to 80 %; VVGG = 7.5 V; Cgate = 2000 pF --30 ns tdch(g) gate discharge time 80 % to 20 %; VVGG = 7.5 V; Cgate = 2000 pF --14 ns Regulated voltage terr(startup) start-up error time of VGG; fosc = 180 MHz - 2.5 - ms tdet(err) error detection time for VGG during operation; fosc = 180 MHz -31.5 - s tfltr(Vo) output voltage filter time for bit Vout1_ok and Vout2_ok; fosc = 180 MHz -31.5 - s tcal calibration time bit VGG_ok = HIGH - - 10 ms |
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