ASL4501SHN datasheet(24/43 Pages) NXP

24 / 43 page

ASL4501SHN

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Product data sheet

Rev. 2 — 10 January 2018

24 of 43

NXP Semiconductors

ASL4501SHN

Four-phase boost converter

8.10.4 Bit Tj_err

The bit Tj_err indicates that the junction temperature has exceeded the maximum

allowable temperature, and the device has entered fail silent mode. A write access to the

diagnostic register, or once off mode has been entered, clears the bit. The device stays in

fail silent mode irrespective of the clearing of the bit. After leaving the off mode (at IC

start-up), it is possible that bit Tj_err is set. To avoid wrong diagnostics, clear the

diagnostic register before it is evaluated.

8.10.5 Bit VGG_err

Bit VGG_err is set when the gate driver does not reach the VGG_ok _window (when VVGG

is within range) within the regulator voltage start-up error time. Once bit VGG_err is set, it

indicates that an error on the gate driver has been detected and the device has entered

fail silent mode. A write access to the diagnostic register, or once off mode has been

entered, clears the bit. The device stays in fail silent mode irrespective of the clearing of

the bit.

8.10.6 Bit VGG_ok

The bit VGG_ok indicates that the gate driver is regulated to the target voltage and allows

the gate drivers to drive the gate driver pins. If the gate driver is outside the VGG_ok

window after tstartup, and VVGG is within range, the device clears VGG_ok bit and enters

fail silent mode.

8.10.7 Bits Vout1_ok and Vout2_ok

The bits Vout1_ok and Vout2_ok indicate whether the output voltage is regulated to the

target value or deviating from the target value. The bits are set as soon as the

corresponding output is within the Vout_ok window (when VO is within the range) for more

than tfltr(ov). The bits are cleared when the corresponding output is outside the Vout_ok

window for more than tfltr(ov).

8.11 SPI

The ASL4501SHN uses an SPI to communicate with an external microcontroller. The SPI

can be used for setting the LEDs current, reading and writing the control register.

8.11.1 SPI introduction

The SPI provides the communication link with the microcontroller, supporting multi-slave

operations. The SPI is configured for full duplex data transfer, so status information is

returned when new control data is shifted in. The interface also offers a read-only access

option, allowing the application to read back the registers without changing the register

content.

The SPI uses four interface signals for synchronization and data transfer:

• CSB - SPI chip select; active LOW

• SCLK - SPI clock - default level is LOW due to low-power concept

• SDI - SPI data input

• SDO - SPI data output - floating when pin CSB is HIGH

Bit sampling is performed on the falling clock edge and data is shifted on the rising clock

edge as illustrated in Figure 8.

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