ASL4501SHN datasheet(30/43 Pages) NXP

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ASL4501SHN

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Product data sheet

Rev. 2 — 10 January 2018

30 of 43

NXP Semiconductors

ASL4501SHN

Four-phase boost converter

8.11.4.2

Configuration registers

The configuration registers inside the control block can only be written in configuration

mode. In the other modes, this register can only be read.

Table 40.

Configuration register group overview

Address Name

Reset

value

02h

gate driver output

00h

O_G4

O_G3

O_G2

O_G1

09h

clock divider for

output 1

0Fh

Clkdiv1[7:0]

0Ah

clock divider for

output 2

0Fh

Clkdiv2[7:0]

0Bh

internal phases

output 1

0Fh

EN_P4_1 EN_P3_1 EN_P2_1 EN_P1_1

0Ch

internal phases

output 2

0Fh

EN_P4_2 EN_P3_2 EN_P2_2 EN_P1_2

0Dh

phase off and delay

output 1

39h

Phdel1[4:0]

Phoff1[2:0]

0Eh

phase off and delay

output 2

39h

Phdel2[4:0]

Phoff2[2:0]

0Fh

gate driver phase

00h

O_GP4

O_GP3

O_GP2

O_GP1

10h

phase selection

configuration

E4h

Phsel4[1:0]

Phsel3[1:0]

Phsel2[1:0]

Phsel1[1:0]

11h

loop filter

proportional

configuration

00h

Prop2[3:0]

Prop1[3:0]

12h

loop filter integral

configuration

00h

Integ2[3:0]

Integ1[3:0]

13h

slope compensation

configuration

88h

Slpcmp2[3:0]

Slpcmp1[3:0]

14h

current sense slope

resistor

configuration

00h

Slpr4[1:0]

Slpr3[1:0]

Slpr2[1:0]

Slpr1[1:0]

15h

gate driver control

FFh

VGG[7:0]

1Ah

overvoltage

detection threshold

FFh

V_VIN_OV[7:0]

1Bh

undervoltage

detection threshold

00h

V_VIN_UV[7:0]

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