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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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DS280DF810ABVT датащи(PDF) 13 Page - Texas Instruments |
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DS280DF810ABVT датащи(HTML) 13 Page - Texas Instruments |
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13 / 51 page  13 DS280DF810 www.ti.com SNLS538A – SEPTEMBER 2016 – REVISED OCTOBER 2019 Product Folder Links: DS280DF810 Submit Documentation Feedback Copyright © 2016–2019, Texas Instruments Incorporated Timing Requirements, Retimer Jitter Specifications (continued) Over operating free-air temperature range (unless otherwise noted). PARAMETER TEST CONDITIONS MIN TYP MAX UNIT JTOL Input jitter tolerance Measured at 28.4 Gbps with SJ frequency > 10 MHz, 29 dB input channel loss, PRBS31 data pattern, 800 mVppd launch amplitude, and 0.078 UIpp total uncorrelated output jitter in addition to the applied SJ. BER < 1E-12. 0.32 UIpp JTOL Input jitter tolerance Measured at 25.78125 Gbps with SJ frequency = 190 KHz, 30 dB input channel loss, PRBS31 data pattern, 800 mVppd launch amplitude, and 0.078 UIpp total uncorrelated output jitter in addition to the applied SJ. BER < 1E-12. 9 UIpp JTOL Input jitter tolerance Measured at 25.78125 Gbps with SJ frequency = 940 KHz, 30 dB input channel loss, PRBS31 data pattern, 800 mVppd launch amplitude, and 0.078 UIpp total uncorrelated output jitter in addition to the applied SJ. BER < 1E-12. 1 UIpp JTOL Input jitter tolerance Measured at 25.78125 Gbps with SJ frequency > 10 MHz, 32 dB input channel loss, PRBS31 data pattern, 800 mVppd launch amplitude, and 0.078 UIpp total uncorrelated output jitter in addition to the applied SJ. BER < 1E-12. 0.38 UIpp TEMPLOCK- CDR stay-in-lock ambient temperature range, negative ramp. Maximum temperature change below initial CDR lock acquisition temperature. 85 °C starting ambient temperature, ramp rate -3 °C/minute, 1.7 liters/sec airflow, 12 layer PCB. 115 °C TEMPLOCK+ CDR stay-in-lock ambient temperature range, positive ramp. Maximum temperature change above initial CDR lock acquisition temperature. -40 °C starting ambient temperature, ramp rate +3 °C/minute, 1.7 liters/sec airflow, 12 layer PCB. 125 °C 7.7 Timing Requirements, Retimer Specifications Over operating free-air temperature range (unless otherwise noted). PARAMETER TEST CONDITIONS MIN TYP MAX UNIT tD Input-to-output latency (propagation delay) through a channel No cross-point; CDR enabled and locked. 3.5UI + 125ps ps tD Input-to-output latency (propagation delay) through a channel Cross-point enabled; CDR enabled and locked. 3.5UI + 145ps ps tD Input-to-output latency (propagation delay) through a channel No cross-point; CDR in raw mode. 25.78125 Gbps data rate. < 145 ps tSK Channel-to-channel inter-pair skew Latency difference between channels at full-rate. 25.78125 Gbps data rate < 30 ps tlock CDR lock acquisition time Measured at 25.78125 Gbps, Adapt Mode = 1 (Reg_0x31[6:5]=0x1), EOM timer = 0x5 (Reg_0x2A[7:4]=0x5). < 100 ms tlock CDR lock acquisition time Measured at 10.3125 Gbps, Adapt Mode = 1 (Reg_0x31[6:5]=0x1), EOM timer = 0x5 (Reg_0x2A[7:4]=0x5). < 100 ms |
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