DS280DF810ABVT datasheet(20/51 Pages) TI1

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DS280DF810

SNLS538A – SEPTEMBER 2016 – REVISED OCTOBER 2019

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Feature Description (continued)

8.3.1.6 Decision Feedback Equalizer (DFE)

A 5-tap DFE can be enabled within the data path of each channel to assist with reducing the effects of cross talk,

reflections, or post cursor inter-symbol interference (ISI). The DFE must be manually enabled, regardless of the

selected adapt mode. Once the DFE has been enabled it can be configured to adapt only during lock acquisition

or to adapt continuously. The DFE can also be manually configured to specified tap polarities and tap weights.

However, when the DFE is configured manually the DFE auto-adaption should be disabled. For many

applications with lower insertion loss (i.e. < 30 dB) lower crosstalk, or lower reflections, part or all of the DFE can

be disabled to reduce power consumption. The DFE can either be fully enabled (taps 1-5), partially enabled (taps

1-2 only), or fully disabled (no taps).

The DFE taps are all feedback taps with 1 UI spacing. Each tap has a specified boost weight range and polarity

bit.

Table 1. DFE Tap Weights

DFE PARAMETER

DECIMAL (REGISTER VALUE)

VALUE (mV) (TYP)

Tap 1 Weight Range

0 - 31

0 – 217

Tap 2-5 Weight Range

0 - 15

0 – 105

Tap Weight Step Size

Polarity

0: (+) positive; feedback value creates a low-pass filter response, thus providing attenuation to

correct for negative-sign post-cursor ISI

1: (-) negative; Feedback value creates a high-pass filter response, thus providing boost to correct

for positive-sign post-cursor ISI.

8.3.1.7 Clock and Data Recovery (CDR)

The CDR consists of a Phase Locked Loop (PLL), PPM counter, and Input and Output Data Multiplexers (mux)

allowing for retimed data, un-retimed data, PRBS generator and output muted modes.

By default, the equalized data is fed into the CDR for clock and data recovery. The recovered data is then output

to the FIR filter and differential driver together with the recovered clock which has been cleaned of any high-

frequency jitter outside the bandwidth of the CDR clock recovery loop. The bandwidth of the CDR defaults to 5.5

MHz (typical) in full-rate (divide-by-1) mode and 5.3 MHz (typical) in sub-rate mode. The CDR bandwidth is

adjustable. Refer to the DS280DF810 Programming Guide for more information on adjusting the CDR bandwidth.

Users can configure the CDR data to route the recovered clock and data to the PRBS checker. Users also have

the option of configuring the output of the CDR to send raw non-retimed data, or data from the pattern generator.

The CDR requires the following in order to be properly configured:

•

25 MHz calibration clock to run the PPM counter (CAL_CLK_IN).

•

Expected data rates must be programmed into the CDR either through the rate table or entered manually with

the corrected divider settings. Refer to the Programming Guide for more information on configuring the CDR

for different data rates.

8.3.1.8 Calibration Clock

The calibration clock is not part of the CDR’s PLL and thus is not used for clock and data recovery. The

calibration clock is connected only to the PPM counter for each CDR. The PPM counter constrains the allowable

lock ranges of the CDR according to the programmed values in the rate table or the manually entered data rates.

The host should provide an input calibration clock signal of 25 MHz frequency. Because this clock is not used for

clock and data recovery, there are no stringent jitter requirements placed on this 25 MHz calibration clock.

8.3.1.9 Differential Driver with FIR Filter

The DS280DF810 output driver has a three-tap finite impulse response (FIR) filter which allows for pre- and post-

cursor equalization to compensate for a wide variety of output channel media. The filter consists of a weighted

sum of three consecutive retimed bits as shown in the following diagram. C[0] can take on values in the range [-

31, +31]. C[-1] and C[+1] can take on values in the range [-15, 15].

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