VDD

ADDR0

ADDR1

SDC

(1)

READ_EN_N

ALL_DONE_N

SDA

(1)

.

.

.

.

.

.

GND

.

.

.

(1) SMBus signals need to be pulled up elsewhere in the system.

.

.

.

Float for SMBus Slave

mode, or connect to next

GHYLFH¶V 5($'

_EN_N for

SMBus Master mode

VDD

1 F

(2x)

0.1 F

(4x)

SMBus Slave

mode

SMBus

Slave mode

2.5 V

.

.

.

EN_SMB

Address straps

(pull-up, pull-down, or float)

1 NŸ

To system SMBus

RX0P

RX0N

TX0P

TX0N

RX1P

RX1N

TX1P

TX1N

CAL_CLK_OUT

CAL_CLK_IN

25 MHz

TEST

2.5 V or 3.3 V

To other open-drain

interrupt pins

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An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,

intellectual property matters and other important disclaimers. PRODUCTION DATA.

DS280DF810

SNLS538A – SEPTEMBER 2016 – REVISED OCTOBER 2019

DS280DF810 28 Gbps Multi-Rate 8-Channel Retimer

1

1 Features

1

•

Octal-Channel Multi-Rate Retimer with Integrated

Signal Conditioning

•

All Channels Lock Independently from 20.2 Gbps

to 28.4 Gbps (Including Sub-Rates Like 10.1376

Gbps, 10.3125 Gbps, 12.5 Gbps, and More)

•

Ultra-Low Latency: <500 ps typical for 28.4 Gbps

data rate

•

Single Power Supply, No Low-Jitter Reference

Clock Required, and Integrated AC Coupling

Capacitors to Reduce Board Routing Complexity

and BOM Cost

•

Integrated 2×2 Cross Point

•

Adaptive Continuous Time Linear Equalizer

(CTLE)

•

Adaptive Decision Feedback Equalizer (DFE)

•

Low-Jitter Transmitter with 3-Tap FIR Filter

•

Combined Equalization Supporting 35+ dB

Channel Loss at 12.9 GHz; 30+ dB Channel Loss

at 14 GHz

•

Adjustable Transmit Amplitude: 205 mVppd to

1225 mVppd (typical)

•

On-Chip Eye Opening Monitor (EOM), PRBS

Pattern Checker/Generator

•

Small 8 mm × 13 mm BGA Package with Easy

Flow-Through Routing

•

Unique Pinout Allows Routing High-Speed Signals

Underneath the Package

•

Pin-Compatible Repeater Available

•

Extended Temperature Range: -40 ºC to 85 ºC

2 Applications

•

Backplane and Mid-plane Reach Extension

•

Jitter Cleaning for Front-Port Optical

•

IEEE802.3bj 100GbE, Infiniband EDR, and OIF-

CEI-25G-LR/MR/SR/VSR Electrical Interfaces

•

SFP28, QSFP28, CFP2/CFP4, CDFP

3 Description

The DS280DF810 is an eight-channel multi-rate

Retimer with integrated signal conditioning. It is used

to extend the reach and robustness of long, lossy,

crosstalk-impaired

high-speed

serial

links

while

Each channel of the DS280DF810 independently

locks to serial data rates in a continuous range from

20.2 Gbps to 28.4 Gbps or to any supported sub-rate

(÷2 and ÷4), including key data rates such as 10.1376

Gbps, 10.3125 Gbps, and 12.5 Gbps, which allows

the DS280DF810 to support individual lane Forward

Error Correction (FEC) pass-through.

Device Information(1)

PART NUMBER

PACKAGE

BODY SIZE (NOM)

DS280DF810

135-pin fcBGA (135) 8.0 mm × 13.0 mm

(1) For all available packages, see the orderable addendum at

the end of the data sheet.

Simplified Schematic