DS280DF810ABVT datasheet(6/51 Pages) TI1

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DS280DF810

SNLS538A – SEPTEMBER 2016 – REVISED OCTOBER 2019

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Pin Functions (continued)

TYPE

INTERNAL

PULL-UP/

PULL-DOWN

DESCRIPTION

NAME

NO.

SMBUS MASTER MODE PINS

READ_EN_N

F13

Input, 3.3 V

LVCMOS

Weak pull-up

SMBus Master Mode (EN_SMB=Float): When asserted low,

initiates the SMBus master mode EEPROM read function. Once

EEPROM read is complete (indicated by assertion of

ALL_DONE_N low), this pin can be held low for normal device

operation. This pin is 3.3 V tolerant.

SMBus Slave Mode (EN_SMB=1): When asserted low, this causes

the device to be held in reset (I2C state machine reset and register

reset). This pin should be pulled high or left floating for normal

operation in SMBus Slave Mode. This pin is 3.3 V tolerant.

ALL_DONE_N

Output,

LVCMOS

None

Indicates the completion of a valid EEPROM register load operation

when in SMBus Master Mode (EN_SMB=Float):

High = External EEPROM load failed or incomplete

Low = External EEPROM load successful and complete

When in SMBus slave mode (EN_SMB=1), this output reflects the

status of READ_EN_N input..

MISCELLANEOUS PINS

INT_N

Output,

LVCMOS,

Open-Drain

None

Open-drain 3.3 V tolerant active-low interrupt output. It pulls low

when an interrupt occurs. The events which trigger an interrupt are

programmable through SMBus registers. This pin can be

connected in a wired-OR fashion with other device's interrupt pin. A

single pull-up resistor in the 2 k

Ω to 5 kΩ range is adequate for the

entire INT_N net.

TEST0

Input, LVCMOS

Weak pull-up

Reserved TI test pins. During normal (non-test-mode) operation,

these pins are configured as inputs and therefore they are not

affected by the presence of a signal. These pins may be left

floating, tied to GND, or connected to a 2.5-V (max) output.

TEST1

E14

Input, LVCMOS

Weak pull-up

TEST4

Input, LVCMOS

Weak pull-up

Reserved TI test pin. During normal (non-test-mode) operation, this

pin is configured as an input and therefore is not affected by the

presence of a signal. This pin should be tied to GND or left floating.

TEST5

Input, LVCMOS

Weak pull-up

Reserved TI test pin. During normal (non-test-mode) operation, this

pin is configured as an input and therefore is not affected by the

presence of a signal. This pin may be left floating, tied to GND, or

connected to a 2.5 V (max) output.

TEST6

Input, LVCMOS

Weak pull-up

TEST7

D12

Input, LVCMOS

Weak pull-up

POWER

VDD

D6, D8, D10,

E5, E6, E7, E8,

E9, E10, F6,

F8, F10

Power

None

Power supply, VDD = 2.5 V ±5%. TI recommends connecting at

least six de-coupling capacitors between the Retimer’s VDD plane

and GND as close to the Retimer as possible. For example, four

0.1 μF capacitors and two 1 μF capacitors directly beneath the

device or as close to the VDD pins as possible.

The VDD pins on this device should be connected through a low-

resistance path to the board VDD plane.

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