RA4W1 datasheet(6/105 Pages) RENESAS

6 / 105 page

R01DS0359EJ0100 Rev.1.00

Page 6 of 105

Mar 31, 2020

RA4W1 Datasheet

1. Overview

Table 1.6

Timers

Feature

Functional description

General PWM Timer (GPT)

The General PWM Timer (GPT) is a 32-bit timer with 4 channels and a 16-bit timer with 3

channels. PWM waveforms can be generated by controlling the up-counter, down-counter, or

the up- and down-counter. In addition, PWM waveforms can be generated for controlling

brushless DC motors. The GPT can also be used as a general-purpose timer. See section 23,

General PWM Timer (GPT) in User’s Manual.

Port Output Enable for GPT (POEG)

Use the Port Output Enable for GPT (POEG) function to place the General PWM Timer (GPT)

output pins in the output disable state. See section 22, Port Output Enable for GPT (POEG) in

User’s Manual.

Asynchronous General Purpose

Timer (AGT)

The Asynchronous General Purpose Timer (AGT) is a 16-bit timer that can be used for pulse

output, external pulse width or period measurement, and counting of external events.

This 16-bit timer consists of a reload register and a down-counter. The reload register and the

down-counter are allocated to the same address, and they can be accessed with the AGT

Realtime Clock (RTC)

The Realtime Clock (RTC) has two counting modes, calendar count mode and binary count

mode, that are controlled by the register settings.

For calendar count mode, the RTC has a 100-year calendar from 2000 to 2099 and

automatically adjusts dates for leap years.

For binary count mode, the RTC counts seconds and retains the information as a serial value.

Binary count mode can be used for calendars other than the Gregorian (Western) calendar.

See section 25, Realtime Clock (RTC) in User’s Manual.

Table 1.7

Communication interfaces (1 of 2)

Feature

Functional description

Serial Communications Interface

(SCI)

The Serial Communication Interface (SCI) is configurable to five asynchronous and

synchronous serial interfaces:

 Asynchronous interfaces (UART and asynchronous communications interface adapter

(ACIA))

 8-bit clock synchronous interface

 Simple IIC (master-only)

 Simple SPI

 Smart card interface.

The smart card interface complies with the ISO/IEC 7816-3 standard for electronic signals and

transmission protocol.

SCI0 and SCI1 have FIFO buffers to enable continuous and full-duplex communication, and

the data transfer speed can be configured independently using an on-chip baud rate generator.

See section 29, Serial Communications Interface (SCI) in User’s Manual.

I2C bus interface (IIC)

The 2-channel I2C bus interface (IIC) conforms with and provides a subset of the NXP I2C

(Inter-Integrated Circuit) bus interface functions. See section 30, I2C Bus Interface (IIC) in

User’s Manual.

Serial Peripheral Interface (SPI)

Two independent Serial Peripheral Interface (SPI) channels are capable of high-speed, full-

duplex synchronous serial communications with multiple processors and peripheral devices.

See section 32, Serial Peripheral Interface (SPI) in User’s Manual.

Controller Area Network (CAN)

module

The Controller Area Network (CAN) module provides functionality to receive and transmit data

using a message-based protocol between multiple slaves and masters in electromagnetically

noisy applications.

The CAN module complies with the ISO 11898-1 (CAN 2.0A/CAN 2.0B) standard and supports

up to 32 mailboxes, which can be configured for transmission or reception in normal mailbox

and FIFO modes. Both standard (11-bit) and extended (29-bit) messaging formats are

supported. See section 31, Controller Area Network (CAN) Module in User’s Manual.

USB 2.0 Full-Speed (USBFS) module The USB 2.0 Full-Speed (USBFS) module can operate as a host controller or device controller.

The module supports full-speed and low-speed (only for the host controller) transfer as defined

in the Universal Serial Bus Specification 2.0. The module has an internal USB transceiver and

supports all of the transfer types defined in the Universal Serial Bus Specification 2.0. The USB

has buffer memory for data transfer, providing a maximum of 10 pipes. Pipes 1 to 9 can be

assigned any endpoint number based on the peripheral devices used for communication or

based on the user system.

The MCU supports revision 1.2 of the Battery Charging Specification. See section 28, USB 2.0

Full-Speed Module (USBFS) in User’s Manual.

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