RA4W1 datasheet(57/105 Pages) RENESAS

57 / 105 page

R01DS0359EJ0100 Rev.1.00

Page 57 of 105

Mar 31, 2020

RA4W1 Datasheet

2. Electrical Characteristics

Figure 2.43

SCI input/output timing in clock synchronous mode

Table 2.35

SCI timing (2)

Parameter

Symbol

Min

Max

Unit

Test conditions

Simple

SPI

SCK clock cycle output (master)

tSPcyc

65536

tPcyc

Figure 2.44

SCK clock cycle input (slave)

65536

SCK clock high pulse width

tSPCKWH

0.4

0.6

tSPcyc

SCK clock low pulse width

tSPCKWL

0.4

0.6

tSPcyc

SCK clock rise and fall time

1.8 V or above

tSPCKr,

tSPCKf

-20

Data input setup

time

Master

2.7 V or above

tSU

Figure 2.45 to

Figure 2.48

2.4 V or above

1.8 V or above

Slave

2.7 V or above

1.8 V or above

Data input hold time Master

33.3

Slave

SS input setup time

tLEAD

tSPcyc

SS input hold time

tLAG

tSPcyc

Data output delay

Master

1.8 V or above

tOD

-40

Slave

2.4 V or above

1.8 V or above

100

Data output hold

time

Master

2.7 V or above

tOH

–10

2.4 V or above

–20

1.8 V or above

–30

Slave

–10

Data rise and fall

time

Master

1.8 V or above

tDr, tDf

-20

Slave

1.8 V or above

Slave access time

tSA

10 (PCLKA >

32 MHz),

6 (PCLKA ≤

32 MHz)

tPcyc

Figure 2.47 and

Figure 2.48

Slave output release time

tREL

10 (PCLKA >

32 MHz),

6 (PCLKA ≤

32 MHz)

tPcyc

tTXD

tRXS tRXH

TXDn

RXDn

SCKn

n = 0, 1, 4, 9

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