RA4W1 datasheet(5/105 Pages) RENESAS

5 / 105 page

R01DS0359EJ0100 Rev.1.00

Page 5 of 105

Mar 31, 2020

RA4W1 Datasheet

1. Overview

Memory Protection Unit (MPU)

Four Memory Protection Units (MPUs) and a CPU stack pointer monitor function are provided

for memory protection. See section 16, Memory Protection Unit (MPU) in User’s Manual.

Watchdog Timer (WDT)

The Watchdog Timer (WDT) is a 14-bit down-counter that can be used to reset the MCU when

the counter underflows because the system has run out of control and is unable to refresh the

WDT. In addition, a non-maskable interrupt or interrupt can be generated by an underflow. The

refresh-permitted period can be set to refresh the counter and used as the condition for

detecting when the system runs out of control. See section 26, Watchdog Timer (WDT) in

User’s Manual.

Independent Watchdog Timer (IWDT)

The Independent Watchdog Timer (IWDT) consists of a 14-bit down-counter that must be

serviced periodically to prevent counter underflow. It can be used to reset the MCU or to

generate a non-maskable interrupt/interrupt for a timer underflow. Because the timer operates

with an independent, dedicated clock source, it is particularly useful in returning the MCU to a

known state as a fail-safe mechanism when the system runs out of control. The IWDT can be

triggered automatically on a reset, underflow, refresh error, or by a refresh of the count value in

the registers. See section 27, Independent Watchdog Timer (IWDT) in User’s Manual.

Table 1.4

Event link

Feature

Functional description

Event Link Controller (ELC)

The Event Link Controller (ELC) uses the interrupt requests generated by various peripheral

modules as event signals to connect them to different modules, enabling direct interaction

between the modules without CPU intervention. See section 19, Event Link Controller (ELC) in

User’s Manual.

Table 1.5

Direct memory access

Feature

Functional description

Data Transfer Controller (DTC)

A Data Transfer Controller (DTC) module is provided for transferring data when activated by an

interrupt request. See section 18, Data Transfer Controller (DTC) in User’s Manual.

DMA Controller (DMAC)

A 4-channel DMA Controller (DMAC) module is provided for transferring data without the CPU.

When a DMA transfer request is generated, the DMAC transfers data stored at the transfer

source address to the transfer destination address. See section 17, DMA Controller (DMAC) in

User’s Manual.

Table 1.3

System (2 of 2)

Feature

Functional description

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