STM8S datasheet(198/467 Pages) STMICROELECTRONICS

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16-bit advanced control timer (TIM1)

RM0016

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DocID14587 Rev 14

17.7.9

Capture/compare mode register 1 (TIM1_CCMR1)

Address offset: 0x08

Reset value: 0x00

This channel can be used in input (capture mode) or in output (compare mode). The

direction of the channel is defined by configuring the CC1S bits. All the other bits of this

function when the channel is configured in output, ICii describes its function when the

channel is configured in input. Therefore, be aware that the same bit can have a different

meaning for the input and output stage.

Bit 2 CC2G: Capture/compare 2 generation

Refer to CC1G description.

Bit 1 CC1G: Capture/compare 1 generation.

This bit is set by software to generate an event. It is automatically cleared by hardware.

0: No action

1: A capture/compare event is generated on channel 1:

If the CC1 channel is configured in output mode:

The CC1IF flag is set and the corresponding interrupt request is sent if enabled.

If the CC1 channel is configured in input mode:

The current value of the counter is captured in the TIM1_CCR1 register. The CC1IF flag is set, and

the corresponding interrupt request is sent if enabled. The CC1OF flag is set if the CC1IF flag is

already high.

Bit 0 UG: Update generation

This bit can be set by software and is automatically cleared by hardware.

0: No action

1: Re-initializes the counter and generates an update of the registers. Note that the prescaler

counter is also cleared. The counter is cleared if center-aligned mode is selected or if DIR = 0 (up-

counting). Otherwise, it takes the auto-reload value (TIM1_ARR) if DIR = 1 (down-counting).

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