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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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STM8S датащи(PDF) 60 Page - STMicroelectronics |
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STM8S датащи(HTML) 60 Page - STMicroelectronics |
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60 / 467 page  Interrupt controller (ITC) RM0016 60/467 DocID14587 Rev 14 Figure 13. Interrupt processing flowchart Caution: If the interrupt mask bits I0 and I1 are set within an interrupt service routine (ISR) with the instruction SIM, removal of the interrupt mask with RIM causes the software priority to be set to level 0. To restore the correct priority when disabling and enabling interrupts inside an ISR, follow the procedures presented in Table 8 for disabling and enabling the interrupts. 6.2.1 Servicing pending interrupts Several interrupts can be pending at the same time. The interrupt to be taken into account is determined by the following two-step process: Table 8. Software priority levels Software priority Level I1 I0 Level 0 (main) Low High 10 Level 1 0 1 Level 2 0 0 Level 3 (= software priority disabled) 1 1 MSv47744V1 RESET PENDING INTERRUPT TRAP TLI I1:0 « IRET » RESTORE PC, X, Y, A, CCR FROM STACK EXECUTE INSTRUCTION STACK PC, X, Y, A, CCR LOAD I1:0 FROM INTERRUPT SW REG. LOAD PC FROM INTERRUPT VECTOR FETCH NEXT INSTRUCTION THE INTERRUPT STAYS PENDING Y N N Y Y N Interrupt has the same or a lower software priority than current one Table 9. Interrupt enabling/disabling inside an ISR Disabling the interrupts Enabling the interrupts #asm PUSH CC POP ISR_CC(1) SIM #endasm 1. ISR_CC is a variable which stores the current value of the CC register. #asm PUSH ISR_CC(1) POP CC #endasm |
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