DP83261AVF datasheet(6/132 Pages) NSC

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20 Architectural Description (Continued)

The Receiver uses these parameters to compare addresses

in incoming frames with its addresses stored in the Parame-

ter RAM

The Transmitter uses the Parameter RAM for generating the

Source Address for all frames (except when Source Ad-

dress Transparency is enabled) and for the Destination Ad-

dress and Information fields in Claim and Beacon frames

The MAC Parameter RAM block is described in greater de-

tails in Section 65

214 CounterTimer

The CounterTimer block maintains all of the Counters and

Timers required by the Standard

Events which occur too rapidly for software to count such

as the various Frame Counts are included in the Event

Counters The size of the wrap around counters has been

chosen to require minimal software intervention even under

marginal operating conditions Most of the Counters incre-

ment in response to events detected by the Receiver The

Counters are readable via the Control Interface

The Token Rotation and Token Holding Timers which are

used to implement the Timed Token Protocol are contained

within the Timer Block

The Counters and Timers are described in detail in Sections

66 and 67

22 INTERFACES

221 PHY Interface

The PHY Intreface is a synchronous interface that provides

an encoded byte stream to the PLAYERa device (the PHY

Request byte stream)

and receives an encoded byte

stream from the PLAYERa device (the PHY Indication byte

stream)

The BMAC device connects to one or two PLAYERa devic-

es via the PH

Indicate and PH

Request Interfaces

Data is transferred from the PLAYERa device to the Ring

Engine via the PH

Indicate Interface Data is transferred

from the Ring Engine to the PLAYERa device via the PH

Request Interface

The 10-bit byte transferred in both directions across the

Indicate and PH

Request interfaces consists of one

parity bit (Odd parity) one Control bit and 8 bits of data

The Control Bit determines if the 8 data bits are a data

symbol pair or a control symbol pair

222 MAC Interface

The MAC Interface provides the required information and

handshakes to allow a system interface (such as the

DP83265A BSI-2) to exploit the capabilities of the Ring En-

gine

The MAC Interface is synchronous and is divided into sepa-

rate MAC Request and MAC Indication interfaces

Data is transferred from the system interface to the Ring

Engine via the MAC Request Interface The MA

Request

Interface consists of a parity bit (Odd parity) and byte-wide

data along with the transmit parameters and handshake sig-

nals The MAC Request Interface utilizes a handshake that

separates token capture from data transmisson A captured

token may be held until it is no longer usable Void frames

are automatically generated to allow data interface logic as

much time as it needs to prepare a transmission

Data is transferred from the Ring Engine to the system inter-

face via the MAC Indication Interface The MA

Indicate

Interface consists of a parity bit (Odd parity) and byte-wide

data along with Addressing Flags and Frame Sequencing

signals The Addressing Flags give the result of the address

comparisons performed by the Ring Engine These are used

to decide whether to continue to copy or to reject frames

The MAC Indication Interface also accepts inputs to deter-

mine how to set the control indicators and increment the

statistical counters based on external address comparison

logic and frame copying logic Frames may also be stripped

based on external comparisons

223 Control Bus Interface

The Control Interface implements the interface to the Con-

trol Bus by which to initialize monitor and diagnose the op-

eration of the BMAC device The Control Interface is an

8-bit asynchronous interface in order to minimize pinout and

layout All information that must be synchronized with the

data stream crosses the MAC Interface

The Control bus is separated completely from the MAC and

PHY Interfaces in order to allow independent operation of

the processor on the Control Bus The Control Interface

provides the synchronization between the Control Bus and

the Ring Engine

30 Feature Overview

The BMAC device implements the standard FDDI MAC pro-

tocol It also provides additional addressing bridging and

service class functions to allow maximal flexibility in design-

ing an FDDI station

The BMAC device offers extensive diagnostic features in-

cluding a number of diagnostic counters a dedicated inter-

face for control and configuration and a capability to per-

form Self Testing Furthermore the BMAC device allows the

tuning of certain parameters to increase the performance of

the network

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