DP83261AVF datasheet(32/132 Pages) NSC

32 / 132 page

60 Control Information (Continued)

64 EVENT REGISTERS

The Event Registers record the occurrence of events or

series of events Events are recorded and contribute to gen-

erating the Interrupt signal There is a two-level hierarchy in

generating this signal

At the first level of the hierarchy events are recorded as bits

in the Latch Registers (eg

Ring Event Latch Registers

Counter Increment Latch Register) Each Latch Register

has a corresponding Mask Register (eg Ring Event Mask

Registers Counter Increment Mask Register) When a bit in

the Latch Register is set to One and its corresponding bit in

the Mask Register is also set to One a bit in the Interrupt

Condition Register is set to One

At the second level of the hierarchy if a bit in the Interrupt

Condition Register is set to One and the corresponding bit

in the Interrupt Mask Register is set to One the Interrupt

signal is asserted

Bits in Conditional Write Registers (eg Ring Event Latch

Registers) are only written when the corresponding bits in

the Compare Register are equal to bits to be overwritten

Servicing Interrupts

In the process of servicing an interrupt a Management Enti-

ty may use one or both levels of condition masks to disable

new interrupts while one is being serviced Soon after the

Management Entity has processed the interrupt to some ex-

tent it is ready to rearm the interrupt in order to be notified

of the next condition

The Interrupt Control Register always contains the merged

output of the masked Condition Registers as shown in

Fig-

ure 6-1 It is only possible to remove a condition by setting

the corresponding Condition Latch Register bit to Zero By

storing the events on-chip and having the ability to selec-

tively set bits to Zero the need for the software to maintain

a copy of the Event Registers is alleviated

To prevent the overwriting and consequent missing of

events an interlock mechanism is used In the period be-

tween the Read of a Condition Latch Register and the cor-

responding Write to reset the condition additional events

can occur

In order to prevent software from overwriting bits which

have changed since the last read and losing interrupt

events a conditional write mechanism is employed Only bits

that have not changed since the last read can be written to

a new value

Whenever a Condition Latch Register is read its contents

are stored in the Compare Register Each bit of the Com-

pare Register is compared with the current contents of the

to a Condition Register is only possible when the corre-

sponding bit in the Compare Register matches the bit in the

Condition Register For any bit that has not changed the

new value of the bit is written into the Register For any bit

that has changed the writing of the bit is inhibited The fact

that an attempt was made to change a modified bit in the

Exception Status Register (ESRCWI)

In the BMAC device the Compare Register is shared by all

of the Condition Latch Registers and always reflects the

most recent read of one of these registers

(In the

DP832515 PLAYER Device there is a Compare Register

for every Event Register) For the cases where more than

one register must be read before writing a new value the

software may write the Compare Register with the most re-

cently read value before writing the register again Alterna-

tively the register may be read again before being written

The Event Registers include the following registers as

Compare Register (CMP)

Current Receiver Status Register (CRS0)

Current Transmitter Status Register (CTS0)

Ring Event Latch Registers (RELR0–1)

Ring Event Mask Registers (REMR0–1)

Token and Timer Event Latch Register (TELR0)

Token and Timer Event Mask Register (TEMR0)

Counter Increment Latch Register (CILR)

Counter Increment Mask Register (CIMR)

Counter Overflow Latch Register (COLR)

Counter Overflow Mask Register (COMR)

Internal Event Latch Register (IELR)

Exception Status Register (ESR)

Exception Mask Register (EMR)

Interrupt Condition Register (ICR)

Interrupt Mask Register (IMR)

TLF10387 – 7

FIGURE 6-1 Event Registers Hierarchy

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