DP83261AVF datasheet(49/132 Pages) NSC

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60 Control Information (Continued)

Interrupt Condition Register (ICR)

The Interrupt Condition Register (ICR) collects unmasked interrupts from the Event Registers Interrupts are categorized into

Ring Events Token and Timer Events Counter Events and Error and Exceptional Status Events If the bit in the Interrupt Mask

Register (IMR) and the corresponding bit in the ICR are set to One the INT pin is forced low and thus triggers an interrupt

Note

Bits are cleared ONLY by clearing underlying conditions (Mask bit andor Event Bit) in the appropriate Event Register

ACCESS RULES

Address

Read

Write

2Eh

Always

Data Ignored

ESE

IERR

RES

COE

CIE

TTE

RNG

Bit

Symbol

Description

RNG

Ring Event Interrupt

Is set if corresponding bits in the Ring Event Latch and Mask Registers are set

TTE

Token and Timer Event Interrupt

Is set if corresponding bits in the Token and Timer Event Latch and

Mask Registers are set

CIE

Counter Increment Event Interrupt

Is set if corresponding bits in the Counter Increment Latch and Mask

Registers are set

COE

Counter Overflow Event Interrupt

Is set if corresponding bits in the Counter Overflow Latch and Mask

Registers are set

D4 – 5

RES

Reserved

IERR

Internal Error Interrupt

Is set if any bits in the Internal Event Register are set

ESE

Exception Status Event Interrupt

Is set if corresponding bits in the Exception Status and Mask Registers

are set

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